PERST (PCIe Reset) in iMX 8M Plus

[Jaiminkumarpatel]

We have iMX6 based SOM which can work as root complex PCIe (master) and iMX 8M plus processor as PCIe End point.

I have sketched a block diagram showing all connections for PCIe signals between both processors. We have PCIe switch which expands main SOM PCIe to multiple PCIe lanes to multiple slots.
Also, we have clock buffer which gets ref clock from main SOM and generates PCIe ref clock for all slots.

The question is regarding PERST (PCIe reset).
- Is this mandatory signal for PCIe endpoint?
- Which pin can work as PCIe rest input for iMX 8M plus processor?

We have mechanism to reset (cold reset) all slots by master (iMX6). But we don't have capability to assign any PCIe specific reset connection due to existing hardware.
- Can we use iMX8M plus cold reset input instead using PCIe specific reset pin (PERST)?
- What is processor ball number for this pin?
- Can you please provide reference of any detailed document regarding this as datasheet doesn't even talk about this function of this Pin?

Thanks!

[JorgeCas]

Hello

- Is this mandatory signal for PCIe endpoint?

Yes, you need this signal for PCIe endpoint.

- Which pin can work as PCIe rest input for iMX 8M plus processor?

Any GPIO could be used for this function. For example, in i.MX8MP EVK board, the pin AA29 is used for this function.

- Can we use iMX8M plus cold reset input instead using PCIe specific reset pin (PERST)

Use the dedicated reset pin function is a better option.

- What is processor ball number for this pin?

The pin AA29 is an example that could be used for that function.

- Can you please provide reference of any detailed document regarding this as datasheet doesn't even talk about this function of this Pin?

This function is not described in reference manual; you could refer to device tree documentation:

https://github.com/nxp-imx/linux-imx/blob/lf-6.6.y/arch/arm64/boot/dts/freescale/imx8mp-evk.dts#L792

Best regards.