PCIe arbitration between SW access and DMA access

[EAlepins]

Hi,

With the i.MX 8X, I am trying to understand what will be the priority / arbitration if 2 access flow are made to the PCIe bus at the same time:

- SW accessing a PCIe memory-mapped zone

- i.MX 8X's PCIe controller DMA performing transfers

The i.MX 8X reference manual does not explain what will happen in this case. For example, if the DMA performs very intensive transfers and links to another DMA channel such that the DMA is continuously active during a long moment (e.g. 1 ms), then will the Cortex-A35 SW access wait during that whole 1 ms?

I am not talking about arbitration between the various DMA channels.

Thanks!

Étienne

[igorpadykov]

Hi Etienne

i.MX 8X has many bus arbiters used for data traffic arbitration between

several masters in the same manner as described in

Chapter 45 Network Interconnect Bus System (NIC-301)

i.MX 6Dual/6Quad Applications Processor Reference Manual

These arbiters modules are different from used in i.MX6Q (NIC-301)

and not intended for customer usage. No information is provided in documentation.

Due to complexity seems it is not possible to predict behaviour for described case:

" example, if the DMA performs very intensive transfers and links to another DMA

channel such that the DMA is continuously active during a long moment (e.g. 1 ms), then will

the Cortex-A35 SW access wait during that whole 1 ms?"

Seems most simple way is to run some test program on i.MX8QXP MEK board with

linux described on

Embedded Linux for i.MX Applications Processors | NXP 

Best regards
igor
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