PCIE link up problem

[thouswave]

Hello.

I am debugging the PCIE unit of our own IMX6Q board,till now,PCIE can not link up.

1.The attach file is our schematic,is there any problem with schematic.For addition,signal PCIE_RST_N and PCIE_PRSNT1 has been checked,and no problem is found.CLK signal is 100M.

2.Our PCIE EP device is (10/100/1000Mbps)NIC，and the Instructions says it supports PCI Express 1.0a。The IMX6Q PCIE PHY support  Revision 2.0 and  Revision 1.1.So if there is some compliance problem?

3.Since we just use the NIC device to check our PCIE unit,so we can choice some other device as well.What is the EP device that freescale use it to check their own board,if I can use it,our develop can be easier.

Any one can help me? Any idea is welcome.

Regards,

[thouswave]

Hi

Thanks for your help.

This problem is solved.We have change the EP device.

Now we use a FPGA board with SPARTAN-6 that produces by our company,and link up successfully.

It just so happens that our next project is a board IM6Q+SPARTAN-6.

[Rita_Wang]

Hi，

It's great news you have solved your problem. :smileyhappy:

Best Regards

Dan

[thouswave]

Hi

Now,our device has been identified,but our device driver can not be install because of the IRQ.

I cat the file /proc/interrupts and find that no pcie IRQ is registed.From IMX6DQRM.pdf,I find IRQ 152-155 is PCIE IRQ.

So,do you have any patch to enable PCIE IRQ,either MSI or INTX is OK.

Thanks.

[Rita_Wang · Accepted solution]

Hi,

Which BSP are you using? I recommend you using the newest L3.0.35_4.1.0_130816_source.tar.gz BSP. And the PCIe clock output should be enabled in the code when the IMX6 worked as RC. Have you enabled the pcie clock yet?

Best Regards

Dan

[thouswave]

Thanks for you reply.

1.For the bsp,I get it from freescale chinese FAE last year,and the BSP name is kernel-3.05.tar.bz2,I can not  get more information about release date.Bypass it, I will download L3.0.35_4.1.0_130816_source.tar.gz and try this afternoon.

2.For the clock enabe,I see it has been enabled in function _clk_cpie_enable.And I have  refer to this https://community.freescale.com/message/380425#380425

[Rita_Wang]

Hi,

You can try to use the newest L3.0.35_4.1.0_130816_source.tar.gz first. And for the clock enabe, refer to that thread is correct. If any problem contact us~~

Best Regards

Dan

[thouswave]

Hi

I have try the new BSP,I config it as PCIE RC mode,unfortunately,PCIE still link down.Following is kernel log:

[    1.628152] cpaddr = ea880000 suspend_iram_base=ea8f0000

[    1.633576] PM driver module loaded

[    1.637175] iMX6 PCIe PCIe RC mode imx_pcie_pltfm_probe entering.

[    1.744760] PCIE: imx_pcie_pltfm_probe start link up.

[    2.355105] link up failed, DB_R0:0x00000602, DB_R1:0x08000000!

[    2.361046] IMX PCIe port: link down!

PS:DR_R0 value is not same every time.

[richard_zhu]

Why pcie rc mode is configured?

As I remember that the explicit PCIE RC/EP modes are used in FSL PCIE RC/EP validation system only.

Richard.

[thouswave]

Thanks for your Attention.

I am sorry that I have not understand your words exactly.I said I config it as RC mode,detail is as following in menuconfig:

System Type   --->

    Freescale MXC Implementations   --->

         [ * ] PCI Express support

         [   ]      PCI Express EP mode in the IMX6 RC/EP interconnection system

         [ * ]     PCI Express RC mode in the IMX6 RC/EP interconnection system

Am I wrong?If my config is wrong,can you tell me the right config.Thanks.

[richard_zhu]

DO NOT select PCI Express RC mode.

Because they are only used in iMX6 PCIe EP/RC validation system.

[ ] PCI Express EP mode in the IMX6 RC/EP interconnection system

[ * ] PCI Express RC mode in the IMX6 RC/EP interconnection system

Enable this one "[ * ] PCI Express support ” is enough at your side.

Richard.

[Rita_Wang]

Hi Hongxing,

Thanks a lot for your help. The customer have solved this problem.

Have a nice day~~

Best Regards

Dan

[thouswave]

Hi

Understand now,I have tried that,but no effect.

I got a new phenomenon.I have two PCIE EP device on hand,different device is inserted,different phenomenon happened.In function {  imx_pcie_link_up  },I add the following source:

ltssm = readl(dbi_base+DB_R0) & 0x3F;

+ printk("0x%.8X,0x%.8X,0x%.8X\n",readl(dbi_base+DB_R0),readl(dbi_base+DB_R1),rx_valid);

if((ltssm == 0xD) && ((rx_valid & 0x1)==0)) {

One EP device's phenomenon is:

[    1.982642] 0x00359E00,0x08200000,0x00000004

[    1.989996] 0x0047D900,0x08200000,0x00000004

[    1.997338] 0x00000602,0x08000000,0x00000002

[    2.004398] 0x004A4A02,0x08000000,0x00000002

[    2.011723] 0x004A4A02,0x08000000,0x00000002

[    2.019069] 0x002CF742,0x08000000,0x00000002

While the other EP device's phenomenon is:

[    1.883904] 0x00590E00,0x08200000,0x00000004

[    1.891322] 0x0050CF00,0x08200000,0x00000004

[    1.898738] 0x002CF742,0x08000000,0x00000006

[    1.905710] 0x004A4A02,0x08000000,0x00000006

[    1.913021] 0x004A4A02,0x08000000,0x00000006

[    1.920340] 0x004ABC43,0x08000000,0x00000006

[    1.927648] 0x00B5BC43,0x08000000,0x00000006

Link training state can be different,so I doubt if some problem with hardware.As I known,PCIE link training state will change as following:

Detect --> Polling --> Configuration --> LO

But now I do not know what is the state now of my board link training.

[Rita_Wang]

Hi richard.zhu, would you please help this issue about "pcie link up problem"?

Thanks a lot~~

Best Regards

Dan

[thouswave]

Hi

I have modify code to print DB_R0 register during tring to link,and I find that xmlh_ltssm_state filed only have one time change:

[    1.982642] 0x00359E00,0x08200000,0x00000004

[    1.989996] 0x0047D900,0x08200000,0x00000004

[    1.997338] 0x00000602,0x08000000,0x00000002

[    2.004398] 0x004A4A02,0x08000000,0x00000002

[    2.011723] 0x004A4A02,0x08000000,0x00000002

[    2.019069] 0x002CF742,0x08000000,0x00000002

Can you tell me what doed the STATE 2 mean?In datasheet,it says [xmlh_ltssm_state LTSSM current state. See source for encodings],I am sorry I still do not know where is [source for encodings].