PCB layout i.MX7D w/ DDR3

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PCB layout i.MX7D w/ DDR3

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tomohisa_sakamo
Contributor V

Hi Support-team,

We have some questions below.

Please support us asap.

See <IMX7DSHDG.pdf>Rev. 0    P19

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Regarding Length for CLK

1.Group:Address and Command       

       1-1.Length Min Clock (min) – 200            => 200mils? ,Is the range within?

       1-2.Length Max Clock(max) Clock (min)1 =>  What is the meaning of "1"?

2.Group:Byte Group 1

      2-1.DQS strobe should have maximum length of Clock -10 mils

       => Is it OK in the judgment of "within" the range of 10 mils?

      2-2.Limit minimum DQS length (lesser of): Clock (min) – 10 mils or 1000mils

       => For example, When CLK = 1500 mils,DQS: 1490 mils or 1000 mils

           Which one should we choose?

           If DQS=1000 mils, there is no relation between DQS and the wiring length of CLK.
           For 1490 mils, we can not understand meaning of above comments.

 

B.Regards

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tomohisa_sakamo
Contributor V

Dear Support team,

Definition:Clock (min) – 200 mils  <= DQS length  <=  Clock (min) – 10 mils


We have additional  one question.

Please refer attached file.(except iMX7DHDG.pdf)


e.g.) CLK 1900mils

         DQS CLK-200mils(MIN)

        DATA DQS-55mils(MIN)

1.It seems that the wiring of the evaluation board and the above relational expression are not kept.
So,we can not understand the relationship between Clk, DQS and DATA.

2.We would like to re-confirm below.

"Match the signals of each byte group ± 55 mils to the strobe. Limit minimum DQS length (lesser of): Clock (min) – 10 mils or 1000mils"

Please support us.

B.Regards,

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  Note, the design rules in the Hardware Guide are still under

considerations (hope will be published soon). Therefore the actual board

implementation may not fully meet all requirements.

  Also, if DQS is shorter than Clock (min) – 200 mils, calibration

should be performed.

Regards,

Yuri.

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tomohisa_sakamo
Contributor V

Dear Yuri-san,

Thank you for your quick reply.

We hope that this content will be reflected in the document renewal.

B.Regards,

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Yuri
NXP TechSupport
NXP TechSupport

We hope that this content will be reflected in the document renewal.

Yes.

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

  Please look at my comments below.

1.

> 1-1.Length Min Clock (min) – 200            => 200mils? ,

    yes, 200 mils

  >     1-2.Length Max Clock(max) Clock (min)1 =>  What is the meaning of "1"?


    just a misprint : "Clock (min)" should be.

2.

  The requirement is as following (to avoid software calibration) :

Clock (min) – 200 mils  <= DQS length  <=  Clock (min) – 10 mils

Have a great day,
Yuri

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