PCA6416 IO Expander IRQ sensitive query in i.MX8MM EVK

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PCA6416 IO Expander IRQ sensitive query in i.MX8MM EVK

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sreedhar_appala
Contributor III

Hi,

I am working with i.MX8MM EVK and Yocto distribution 4.19 imx-warrior version.

from the below post, i am able to generate the level sensitive interrupts.

https://community.nxp.com/t5/i-MX-Processors/How-to-enable-interrupts-of-EXP-GPIOs-from-PCA6416-in-I...

The driver code gpio-pca953x.c is registering the IRQ as 

ret = devm_request_threaded_irq(&client->dev,
                                                      client->irq,
                                                      NULL,
                                                      pca953x_irq_handler,
                                                      IRQF_TRIGGER_LOW | IRQF_ONESHOT |
                                                      IRQF_SHARED,
                                                      dev_name(&client->dev), chip);

From the datasheet of pca6416, section 7.8

..................................................................................................................

The INT output has an open-drain structure and requires pull-up resistor to VDD(P) or
VDD(I2C-bus) depending on the application. INT should be connected to the voltage source
of the device that requires the interrupt information

..................................................................................................................

1. Is it possible to generate the Rising Edge interrupts in PCA6416 IO Expander?

2. Does open-drain nature of INT pin allows Rising Edge Interrupt instead of Level sensitive interrupts?

Thank you, Sreedhar

@weidong_sun 

 

 

 

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2 Replies

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art
NXP TechSupport
NXP TechSupport

1. The "level" or "edge" sensitive interrupts are handled on the interrupt
hadler (not source) side depending on what exactly event the interrupt handler
side wants to detect according to the interrupt source operational logic.

The PCA6416 Data Sheet document describes the INT# signal operational logic as follows.

"An interrupt is generated by any rising or falling edge of the port inputs in
the Input mode. After time tv(INT), the signal INT is valid. The interrupt is
reset when data on the port changes back to the original value or when data is
read from the port that generated the interrupt. Resetting occurs in the Read
mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising
edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse
can be lost (or be very short) due to the resetting of the interrupt during this
pulse. Any change of the I/Os after resetting is detected and is transmitted as
INT."

2. The physical type of interrupt signal output (open-drain or actively driven) has no
matter to interprete the interrupt source operational logic, see above.

Best Regards,
Artur

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sreedhar_appala
Contributor III

Hi,

Could you please respond to my query?

Thank you, Sreedhar

@Igor 

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