PAD_ENET1_TX_CLK & PAD_ENET2_TX_CLK control register not properly documented?

[Oleh]

I have a question about ENET1_TX_CLK & ENET2_TX_CLK control registers.
I see that in most cases, it uses a 0x400XXXXX value. Here an example:

imx6ul-14x14-evk.dtsi: MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
imx6ul-14x14-evk.dtsi: MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031

But what 30-bit means?
Documentation doesn't define 30-bit:

[Yuri · Accepted solution]

@Oleh 
Hello,

  the following clarifies the issue:

https://community.nxp.com/t5/i-MX-Processors/Why-the-difference-between-mex-reference-design-and-Lin...

Regards,
Yuri.