Operating points on imx6sx SabreSD DTS

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Operating points on imx6sx SabreSD DTS

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maurosalvini
Contributor II

Hi,

I'm doing some modifications on imx6sx SabreSD dts to tailor it on my custom board.

On cpu0 section of imx6sx.dtsi file I can find these operating points:

operating-points = <
   /* kHz uV */
   996000 1250000
   792000 1175000
   396000 1075000
   198000 975000
>;
fsl,soc-operating-points = <
   /* ARM kHz SOC uV */
   996000 1175000
   792000 1175000
   396000 1175000
   198000 1175000
>;


used for reg_arm and reg_soc respectively. These settings come from table 10 in IMX6SXCEC.pdf, the imx6sx datasheet.


In imx6sx-sdb.dts file these settings are overwrited with these ones:

operating-points = <
   /* kHz uV */
    996000 1250000
    792000 1175000
    396000 1175000
    198000 1175000
>;
fsl,soc-operating-points = <
   /* ARM kHz SOC uV */
    996000 1250000
    792000 1175000
    396000 1175000
    198000 1175000
>;


both referred to sw1a_reg (SW1AB regulator into PFuze200 that is on SabreSD board).

These values puzzles me in some way: I can understand that the two tables have same values because PFuze power source is shared between ARM domain and SOC domain, but values are strange to me, and I try to explain why.

On datasheet, into LDO enabled section, we have this assertion:

"VDDARM_IN must be 125mV higher than the LDO Output Set Point (VDD_ARM_CAP) for correct supply voltage regulation."

ARM and SOC LDOs are programmed to 1.150V and 1.175V respectively (I read 0x020c8140 register that has 0x004c0012 value, see PMU_REG_CORE into imx6sx reference manual; 1.175V set by u-boot), so I would expect that on input we must have at least 1.3V.

Aren't these values wrong? If they are correct, what is the reason?

I'm using u-boot and kernel form latest commit on meta-fsl-arm repo from Yocto project, branch Krogoth.

Thanks in advance, regards

Mauro

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art
NXP Employee
NXP Employee

Actually, the set points for the PMIC are correct. The set points for the SoC internal LDOs are not used on the early boot stage, but the LDOs are switched to bypass mode instead. Further, the LDO set points are used by kernel for power saving management.


Have a great day,
Artur

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art
NXP Employee
NXP Employee

Actually, the set points for the PMIC are correct. The set points for the SoC internal LDOs are not used on the early boot stage, but the LDOs are switched to bypass mode instead. Further, the LDO set points are used by kernel for power saving management.


Have a great day,
Artur

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maurosalvini
Contributor II

Hi Artur,

yes, you are right.

What you describe happens on u-boot from freescale git tree, that reads fsl,ldo-bypass property into device tree and set LDO bypass; I was watching u-boot from meta-fsl-arm Yocto layer, maintained by community, that does not do that.

I have to move this question to meta-freescale community.

Thank you, regards.

Mauro

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