Observing half clock when accessing Quad SPI and Octal SPI memories in DDR mode

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Observing half clock when accessing Quad SPI and Octal SPI memories in DDR mode

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priyank_bhatt
Contributor III

Hello,

 

We are using iMX8QXP MEK based custom board with Yocto L5.4.24-2.1.0. In our project, we are connecting multiple memories(like Octal SPI flash, Quad SPI flash, Octal SPI RAM) on the FlexSPI interface.

Our aim is to access these memories at the maximum possible speed. During read-write testing, we noticed that in SDR mode we are able to read-write memories at the clock frequency which we have set in the device tree file(spi-max-frequency property) but in DDR mode the frequency is halved.

In the reference manual, we have seen the table 18.4 below which clearly states that the clock will be halved in DDR mode.

priyank_bhatt_0-1604575130331.png

 

Also, the waveforms in the reference manual show half clock in DDR operations

priyank_bhatt_1-1604575130089.png

priyank_bhatt_2-1604575130504.png

From all these data from the reference manual, we understand that when we access memories in SDR mode the clock remains the same, but when we access memories in DDR mode the clock will get halved.

If the clock reduces by half during DDR, the actual data rate remains the same as during SDR and our actual goal of achieving the maximum data rate is not fulfilled.

1. Is this behavior correct?

In the IMX8QXPAEC document, we have read the following under FlexSPI timing parameters. 

priyank_bhatt_3-1604575130187.png

2. Does this mean that we can access memories in DDR mode with the same frequency as SDR mode by changing MCR0[RXCLKSRC] register bits?

3. If yes, is there any document/procedure for that?

Thank you

Priyank

11 Replies

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi priyank_bhatt

 

I think you are right, frequency can be changed using MCR0[RXCLKSRC] register

as described in Table 99-101 FlexSPI timings with FlexSPIn_MCR0

i.MX 8QuadXPlus and 8DualXPlus Automotive and Infotainment Applications Processors

 

Best regards
igor

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381 Views
priyank_bhatt
Contributor III

He @igorpadykov 

Thanks for the quick reply. I am a bit confused about that MCRO[RXCLKSRC].

Because when I tried to change RXCLKSRC to 0x3 in flexSPI driver I observed kernel panic. Then after looking into the reference manual I found this statement

priyank_bhatt_0-1604726020652.png

Thah is why I am asking if there is any document or procedure which I can follow to achieve proper clock?

 

Thank you.

Priyank

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Priyank

 

I am afraid you can not manually change frequency, as for example in

case for spi-nor usage, it is selected automatically by spi-nor driver

reading memory capabilities as described in JESD216 SFDP  specification

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/mtd/spi-nor/spi-nor.c?h=imx_5.4.47...

 

Best regards
igor

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priyank_bhatt
Contributor III

Hi @igorpadykov 

As per the reference manual

Screenshot from 2020-10-23 10-29-17.png

We are observing that in SDR mode we are getting the same clock frequency as serial clock and half clock frequency in DDR mode.

Is this the expected behavior?

 

Thank you.

Priyank

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igorpadykov
NXP TechSupport
NXP TechSupport

>Is this the expected behavior?

 

probably linux driver selects mode which is supported by that particular

spi-nor, one can try to debug fspi driver using AN 12631

Normal and Secure Debug for i.MX8/8X Family of Applications Processors

 

Best regards
igor

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299 Views
priyank_bhatt
Contributor III

Hello,

I think there is some misunderstanding. I will again ask my query

As per reference manual IMX8DQXPRM Rev. E Table 18-4, it is mentioned that half clock frequency in DDR mode and the same frequency as the serial clock in SDR mode. We are also observing the same behavior.


Is this the expected behavior?

 

Thank you

Priyank

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igorpadykov
NXP TechSupport
NXP TechSupport

Hello

 

> it is mentioned that half clock frequency in DDR mode and the same frequency as the serial clock in SDR mode.

 

sorry this is not true, actually it describes:

Half clock frequency of serial clock root in DDR
mode, and same frequency as serial clock root in
SDR mode.

 

Serial clock root is not clock which you are observing.

 

>Is this the expected behavior?

 

in theory it should work as described in Reference Manual.

In real life it depends on many factors: used driver, operating system and attached devices.

In particular Reference Manual describes it :

 

1.jpg

 

Best regards
igor

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priyank_bhatt
Contributor III

Hi @igorpadykov 

Thank you for your reply.

With the driver(spi_nor.c), operating system(Yocto L5.4.24-2.1.0) and Octal flash, Octal RAM, Octal MCP devices we observed that the frequency in DDR mode is getting halved compared to SDR mode frequency as mentioned in the reference manual.

Are there any changes we can do to get the same clock frequency in SDR and DDR mode?

 

Thank you.

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igorpadykov
NXP TechSupport
NXP TechSupport

had you verified with qspi datasheet, that its declared ddr mode frequency is more high

than observed ?

 

Best regards
igor

 

 

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priyank_bhatt
Contributor III

Hi @igorpadykov 

The maximum supported clock frequency is 200MHz. Our main aim is to access memories with the same clock which we set in dts node.
But when we set max-spi-frequency as 200MHz in dts node and operate with DDR mode we only observe 100MHz on QSPI0A_SCLK pin.

 

Regards

Priyank

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Priyank

 

"set max-spi-frequency as 200MHz in dts" does not guarantee that part will operate at 200MHz.

Operating frequency is selected by reading qspi-nor capability as described in Linux Manual

 

1.jpg

so spi-nor.c driver reads Serial Flash Discoverable Parameters (SFDP) and sets operating frequency

according to data obtained from qspi-nor:

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/mtd/spi-nor/spi-nor.c?h=imx_5.4.47...

http://www.macronix.com/Lists/ApplicationNote/Attachments/1870/AN114v1-SFDP%20Introduction.pdf

 

Best regards
igor

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