ODT configuration of IMX6Q and DDR3L side

[Sadatan123]

Given below is the DCD file details of the IMX6Q. Can someone let me know what are the configuration for different signals like Data lines, strobe etc as per this code. Specially data in read and write mode

//DDR IO TYPE:
DCD_ENTRY(1, 0x020e0798, 0x000C0000) // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
DCD_ENTRY(2, 0x020e0758, 0x00000000) // IOMUXC_SW_PAD_CTL_GRP_DDRPKE

//CLOCK:
DCD_ENTRY(3, 0x020e0588, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
DCD_ENTRY(4, 0x020e0594, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1

//ADDRESS:
DCD_ENTRY(5, 0x020e056c, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
DCD_ENTRY(6, 0x020e0578, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
DCD_ENTRY(7, 0x020e074c, 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_ADDDS

//Control:
DCD_ENTRY(8, 0x020e057c, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
DCD_ENTRY(9, 0x020e058c, 0x00000000) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
DCD_ENTRY(10, 0x020e059c, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
DCD_ENTRY(11, 0x020e05a0, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
DCD_ENTRY(12, 0x020e078c, 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_CTLDS

//Data Strobes:
DCD_ENTRY(13, 0x020e0750, 0x00020000) // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
DCD_ENTRY(14, 0x020e05a8, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
DCD_ENTRY(15, 0x020e05b0, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
DCD_ENTRY(16, 0x020e0524, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
DCD_ENTRY(17, 0x020e051c, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3

//Data:
DCD_ENTRY(18, 0x020e0774, 0x00020000) // IOMUXC_SW_PAD_CTL_GRP_DDRMODE
DCD_ENTRY(19, 0x020e0784, 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_B0DS
DCD_ENTRY(20, 0x020e0788, 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_B1DS
DCD_ENTRY(21, 0x020e0794, 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_B2DS
DCD_ENTRY(22, 0x020e079c, 0x00000030) // IOMUXC_SW_PAD_CTL_GRP_B3DS

DCD_ENTRY(23, 0x020e05ac, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
DCD_ENTRY(24, 0x020e05b4, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
DCD_ENTRY(25, 0x020e0528, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
DCD_ENTRY(26, 0x020e0520, 0x00000030) // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3

//=============================================================================
// DDR Controller Registers
//=============================================================================
// Manufacturer: Micron
// Device Part Number: MT41K512M16HA-125
// Clock Freq.: 528MHz
// Density per CS in Gb: 16
// Chip Selects used: 1
// Number of Banks: 8
// Row address: 16
// Column address: 10
// Data bus width 32
//=============================================================================
DCD_ENTRY(27, 0x021b001c, 0x00008000) //MMDC0_MDSCR, set the Configuration request bit during MMDC set up

//=============================================================================
// Calibration setup.
//=============================================================================
DCD_ENTRY(28, 0x021b0800, 0xA1390003) // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.

// For target board, may need to run write levelling calibration to fine tune these settings.
DCD_ENTRY(29, 0x021b080c, 0x002D003A) // MMDC1_MPWLDECTRL0
DCD_ENTRY(30, 0x021b0810, 0x0038002B) // MMDC1_MPWLDECTRL1

//Read DQS Gating calibration
DCD_ENTRY(31, 0x021b083c, 0x03340338) // MPDGCTRL0 PHY0
DCD_ENTRY(32, 0x021b0840, 0x0334032C) // MPDGCTRL1 PHY0

//Read calibration
DCD_ENTRY(33, 0x021b0848, 0x4036383C) // MPRDDLCTL PHY0

//Write calibration
DCD_ENTRY(34, 0x021b0850, 0x2E384038) // MPWRDLCTL PHY0

//read data bit delay: (3 is the recommended default value, although out of reset value is 0)
DCD_ENTRY(35, 0x021b081c, 0x33333333) // DDR_PHY_P0_MPREDQBY0DL3
DCD_ENTRY(36, 0x021b0820, 0x33333333) // DDR_PHY_P0_MPREDQBY1DL3
DCD_ENTRY(37, 0x021b0824, 0x33333333) // DDR_PHY_P0_MPREDQBY2DL3
DCD_ENTRY(38, 0x021b0828, 0x33333333) // DDR_PHY_P0_MPREDQBY3DL3

// Complete calibration by forced measurement:
DCD_ENTRY(39, 0x021b08b8, 0x00000800) // DDR_PHY_P0_MPMUR0, frc_msr
//=============================================================================
// Calibration setup end
//=============================================================================

//MMDC init:
DCD_ENTRY(40, 0x021b0004, 0x00020036) // MMDC0_MDPDC
DCD_ENTRY(41, 0x021b0008, 0x09444040) // MMDC0_MDOTC
DCD_ENTRY(42, 0x021b000c, 0xB8BE7955) // MMDC0_MDCFG0
DCD_ENTRY(43, 0x021b0010, 0xFF328F64) // MMDC0_MDCFG1
DCD_ENTRY(44, 0x021b0014, 0x01FF00DB) // MMDC0_MDCFG2

//MDMISC: RALAT kept to the high level of 5.
//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
//b. Small performance improvement
DCD_ENTRY(45, 0x021b0018, 0x00011740) // MMDC0_MDMISC
DCD_ENTRY(46, 0x021b001c, 0x00008000) // MMDC0_MDSCR, set the Configuration request bit during MMDC set up
DCD_ENTRY(47, 0x021b002c, 0x000026D2) // MMDC0_MDRWD
DCD_ENTRY(48, 0x021b0030, 0x00BE1023) // MMDC0_MDOR
DCD_ENTRY(49, 0x021b0040, 0x00000047) // Chan0 CS0_END
DCD_ENTRY(50, 0x021b0000, 0x85190000) // MMDC0_MDCTL

//Mode register writes
DCD_ENTRY(51, 0x021b001c, 0x00888032) // MMDC0_MDSCR, MR2 write, CS0
DCD_ENTRY(52, 0x021b001c, 0x00008033) // MMDC0_MDSCR, MR3 write, CS0
DCD_ENTRY(53, 0x021b001c, 0x00008031) // MMDC0_MDSCR, MR1 write, CS0
DCD_ENTRY(54, 0x021b001c, 0x19408030) // MMDC0_MDSCR, MR0write, CS0
DCD_ENTRY(55, 0x021b001c, 0x04008040) // MMDC0_MDSCR, ZQ calibration command sent to device on CS0

DCD_ENTRY(56, 0x021b0020, 0x00007800) // MMDC0_MDREF

DCD_ENTRY(57, 0x021b0818, 0x00000007) // DDR_PHY_P0_MPODTCTRL

[JorgeCas]

Hello,

The IOMUXC_SW_PAD_CTL_PAD_* registers are used to configure the electrical characteristics of the pad.

You can check the value configuration in reference manual.

Best regards.