Not able to driver high on UPLL_BYPCLK with ALT5 using i.mx25

[suzan]

Hi,

I am working on iMX258. I want to drive high and low on UPLL_BYPCLK line. I

configured this line with ALT5 functionality (GPIO), Since there is no PAD

configuration register for this line my level change doesn't effect the environment.

How can I drive different level on the pin UPLL_BYPCLK (GPIO[16]).

Regards,

suzan

[jimmychan · Accepted solution]

According to the i.MX25RM Table 4-18, UPLL_BYPCLK is only DVS can be configured.

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Hysteresis Enable—Disabled

Drive Strength—Nominal

Pull/Keep Enable—Disabled

Pull Up/Down Configuration—100 KΩ PU

Open Drain Enable—Disabled

Drive Voltage Select—CFG (3.3 V)

Pull/Keep Select—Keep

Slew Rate—FAST

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By default, the DVS is 3.3V.

You can change the setting in (Offset 0x0434) (IOMUXC_SW_PAD_CTL_GRP_DVS_CRM)

Please check if you set it correct.