No transmit data from audmux on i.MX6

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

No transmit data from audmux on i.MX6

1,465 Views
marksatterfield
Contributor I

My current configuration is I have setup dma data to the SSI2 TX FIFO and I have setup port3 to recv data from port2 and the port3 physical connections are to a Audio Codec (acting as I2S master) where I am getting the TXC and TXFS clocks from the audio codec. I see data being transferred from the SSI2 TX FIFO to the TX register via the TX SISR register but no data is being transmitter on the TXD from the aud mux.

Init setting on aud mux:

// Get pointers to the Audio MUX internal port registers.


pPTCR = &m_pAUDMUX->PTCR1 + intPort * 2;
pPDCR = &m_pAUDMUX->PDCR1 + intPort * 2;

// All clock signals for the internal port are all output signals for
// Codec master mode.


OUTREG32(pPTCR,
CSP_BITFVAL(AUDMUX_PTCR_TFSDIR, AUDMUX_PTCR_TFSDIR_OUTPUT) |
CSP_BITFVAL(AUDMUX_PTCR_TFSEL, extPort) |
CSP_BITFVAL(AUDMUX_PTCR_TCLKDIR, AUDMUX_PTCR_TCLKDIR_OUTPUT) |
CSP_BITFVAL(AUDMUX_PTCR_TCSEL, extPort) |
CSP_BITFVAL(AUDMUX_PTCR_SYN, AUDMUX_PTCR_SYN_SYNC));

OUTREG32(pPDCR,
   CSP_BITFVAL(AUDMUX_PDCR_RXDSEL, extPort) |
   CSP_BITFVAL(AUDMUX_PDCR_TXRXEN, AUDMUX_PDCR_TXRXEN_NO_SWAP) |
   CSP_BITFVAL(AUDMUX_PDCR_MODE, AUDMUX_PDCR_MODE_NORMAL));

// Get pointers to the Audio MUX external port registers.


pPTCR = &m_pAUDMUX->PTCR1 + extPort * 2;
pPDCR = &m_pAUDMUX->PDCR1 + extPort * 2;

// All clock signals for the external port are input signals for
// Codec master mode.
OUTREG32(pPTCR,
   CSP_BITFVAL(AUDMUX_PTCR_TFSDIR, AUDMUX_PTCR_TFSDIR_INPUT) |
   CSP_BITFVAL(AUDMUX_PTCR_TCLKDIR, AUDMUX_PTCR_TCLKDIR_INPUT) |
   CSP_BITFVAL(AUDMUX_PTCR_SYN, AUDMUX_PTCR_SYN_SYNC));

OUTREG32(pPDCR,
   CSP_BITFVAL(AUDMUX_PDCR_RXDSEL, intPort) |
   CSP_BITFVAL(AUDMUX_PDCR_TXRXEN, AUDMUX_PDCR_TXRXEN_NO_SWAP) |
   CSP_BITFVAL(AUDMUX_PDCR_MODE, AUDMUX_PDCR_MODE_NORMAL));

BSPAudioIomuxConfig();

aud mux settings:

#include "iomux_config.h"
#include "registers/regsiomuxc.h"

// Function to configure IOMUXC for audmux module.
void audmux_iomux_config(void)
{
// Config audmux.AUD3_RXD to pad CSI0_DATA07(N3)
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_WR(0x00000004);
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR(0x0001B0B0);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07(0x020E0080)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA07
// ALT1 (1) - Select instance: eim signal: EIM_DATA05
// ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_SS0
// ALT3 (3) - Select instance: kpp signal: KEY_ROW6
// ALT4 (4) - Select instance: audmux signal: AUD3_RXD
// ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO25
// ALT7 (7) - Select instance: arm signal: ARM_TRACE04
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_WR(
      BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_SION_V(DISABLED) |
      BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07_MUX_MODE_V(ALT4));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07(0x020E0394)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// RESERVED0 (0) - Reserved
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_WR(
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_HYS_V(ENABLED) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUS_V(100K_OHM_PU) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PUE_V(PULL) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_PKE_V(ENABLED) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_ODE_V(DISABLED) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SPEED_V(100MHZ) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_DSE_V(40_OHM) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07_SRE_V(SLOW));

// Config audmux.AUD3_TXC to pad CSI0_DATA04(N1)
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_WR(0x00000004);
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR(0x0001B0B0);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04(0x020E0074)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA04
// ALT1 (1) - Select instance: eim signal: EIM_DATA02
// ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_SCLK
// ALT3 (3) - Select instance: kpp signal: KEY_COL5
// ALT4 (4) - Select instance: audmux signal: AUD3_TXC
// ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO22
// ALT7 (7) - Select instance: arm signal: ARM_TRACE01
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_WR(
      BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_SION_V(DISABLED) |
      BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04_MUX_MODE_V(ALT4));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04(0x020E0388)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// RESERVED0 (0) - Reserved
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_WR(
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_HYS_V(ENABLED) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUS_V(100K_OHM_PU) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PUE_V(PULL) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_PKE_V(ENABLED) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_ODE_V(DISABLED) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SPEED_V(100MHZ) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_DSE_V(40_OHM) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04_SRE_V(SLOW));

// Config audmux.AUD3_TXD to pad CSI0_DATA05(P2)
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_WR(0x00000004);
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR(0x0001B0B0);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05(0x020E0078)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA05
// ALT1 (1) - Select instance: eim signal: EIM_DATA03
// ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_MOSI
// ALT3 (3) - Select instance: kpp signal: KEY_ROW5
// ALT4 (4) - Select instance: audmux signal: AUD3_TXD
// ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO23
// ALT7 (7) - Select instance: arm signal: ARM_TRACE02
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_WR(
      BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_SION_V(DISABLED) |
      BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05_MUX_MODE_V(ALT4));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05(0x020E038C)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// RESERVED0 (0) - Reserved
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_WR(
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_HYS_V(ENABLED) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUS_V(100K_OHM_PU) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PUE_V(PULL) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_PKE_V(ENABLED) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_ODE_V(DISABLED) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SPEED_V(100MHZ) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_DSE_V(40_OHM) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05_SRE_V(SLOW));

// Config audmux.AUD3_TXFS to pad CSI0_DATA06(N4)
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_WR(0x00000004);
// HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR(0x0001B0B0);
// Mux Register:
// IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06(0x020E007C)
// SION [4] - Software Input On Field Reset: DISABLED
// Force the selected mux mode Input path no matter of MUX_MODE functionality.
// DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
// ENABLED (1) - Force input path of pad.
// MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
// Select iomux modes to be used for pad.
// ALT0 (0) - Select instance: ipu1 signal: IPU1_CSI0_DATA06
// ALT1 (1) - Select instance: eim signal: EIM_DATA04
// ALT2 (2) - Select instance: ecspi1 signal: ECSPI1_MISO
// ALT3 (3) - Select instance: kpp signal: KEY_COL6
// ALT4 (4) - Select instance: audmux signal: AUD3_TXFS
// ALT5 (5) - Select instance: gpio5 signal: GPIO5_IO24
// ALT7 (7) - Select instance: arm signal: ARM_TRACE03
HW_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_WR(
BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_SION_V(DISABLED) |
BF_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06_MUX_MODE_V(ALT4));
// Pad Control Register:
// IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06(0x020E0390)
// HYS [16] - Hysteresis Enable Field Reset: ENABLED
// DISABLED (0) - CMOS input
// ENABLED (1) - Schmitt trigger input
// PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
// 100K_OHM_PD (0) - 100K Ohm Pull Down
// 47K_OHM_PU (1) - 47K Ohm Pull Up
// 100K_OHM_PU (2) - 100K Ohm Pull Up
// 22K_OHM_PU (3) - 22K Ohm Pull Up
// PUE [13] - Pull / Keep Select Field Reset: PULL
// KEEP (0) - Keeper Enabled
// PULL (1) - Pull Enabled
// PKE [12] - Pull / Keep Enable Field Reset: ENABLED
// DISABLED (0) - Pull/Keeper Disabled
// ENABLED (1) - Pull/Keeper Enabled
// ODE [11] - Open Drain Enable Field Reset: DISABLED
// Enables open drain of the pin.
// DISABLED (0) - Output is CMOS.
// ENABLED (1) - Output is Open Drain.
// SPEED [7:6] - Speed Field Reset: 100MHZ
// RESERVED0 (0) - Reserved
// 50MHZ (1) - Low (50 MHz)
// 100MHZ (2) - Medium (100 MHz)
// 200MHZ (3) - Maximum (200 MHz)
// DSE [5:3] - Drive Strength Field Reset: 40_OHM
// HIZ (0) - HI-Z
// 240_OHM (1) - 240 Ohm
// 120_OHM (2) - 120 Ohm
// 80_OHM (3) - 80 Ohm
// 60_OHM (4) - 60 Ohm
// 48_OHM (5) - 48 Ohm
// 40_OHM (6) - 40 Ohm
// 34_OHM (7) - 34 Ohm
// SRE [0] - Slew Rate Field Reset: SLOW
// Slew rate control.
// SLOW (0) - Slow Slew Rate
// FAST (1) - Fast Slew Rate
HW_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_WR(
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_HYS_V(ENABLED) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUS_V(100K_OHM_PU) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PUE_V(PULL) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_PKE_V(ENABLED) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_ODE_V(DISABLED) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SPEED_V(100MHZ) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_DSE_V(40_OHM) |
      BF_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06_SRE_V(SLOW));
}

Any ideas why I can get the data from port 3 AudMux output?

Tags (2)
0 Kudos
8 Replies

1,081 Views
marksatterfield
Contributor I

I switched back to having the WM8962 Audio Codec as the i2s master and I see a transmit frame sync signal now at 56 khz but still getting no transmit data from the i.MX audio mux?

0 Kudos

1,081 Views
marksatterfield
Contributor I

I now have a TX FS running at 44.1 KHz and a bit clock (TXC) going to the aud mux port 3 interface on the i.MX but when the application sends data to SSI2 I see the TX FIFOs get filled and when TE is enabled on the SSI2 interface I see 1 message from TX0 FIFO get put in the TX register and then everything stops. Looks like frame sync and/or TXC is not being feed from aud mux port 3 to aud mux port 2? Any ideas?

0 Kudos

1,081 Views
igorpadykov
NXP Employee
NXP Employee

Hi Mark

what processor used in the case, for example i.MX6DQ SSI-AUDMUX numbering

is provided in Table 85. AUDMUX Port Allocation i.MX6DQ Datasheet

http://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf

for routing signals from SSI to AUDMUX one can look at baremetal examples in SDK

Github SDK
https://github.com/backenklee/swp-report/tree/master/iMX6_Platform_SDK

Please use AUDMUX Chapter in Reference Manual for particular processor, AUDMUX_PTCRn description.

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos

1,081 Views
marksatterfield
Contributor I

Processor is a iMX6Q SABRE SD DL. I see that the Audio Codec is supplying a TX clock and frame sync signal and I see the data being transferred from the TX FIFO to the TX register in the SSI but no data is getting sent from port 3 to the audio codec. I will look the baremetal example. I am using DMA to populate the TX FIFOs in SSI2 interface.

I am trying to switch things around and make the Audio Codec connected to port 3 a slave and have the SSI2 be the master in the config so instead of using the Audio Codec

to drive the TX Bit Clock and Frame Sync I am using the SSI internal clocks. I am using IMX6SDLRM.pdf as my reference manual.

0 Kudos

1,081 Views
igorpadykov
NXP Employee
NXP Employee
0 Kudos

1,081 Views
marksatterfield
Contributor I

Now that I switched the SSI to master mode and I have switched the ports configuration I am seeing a bit clock coming out of port 3 but no Tx frame sync or Tx data. I do see the application is continually sending data where before the application would send the data until the DMA was full and then stop. My audio codec is a WM8962 so I believe I need to set the SSI bit clock and frame sync signal frequencies lower but shouldn't I see some tx frame sync and tx data even if the frequencies are too high? TXC clock is running a 1.9 MHz right now.

0 Kudos

1,081 Views
igorpadykov
NXP Employee
NXP Employee

frame sync can be easily debugged using sect.Figure 61-23. SSI Transmit Frame Sync

Generator Block Diagram i.MX6DQ RM and printf (or check with jtag) some sync related ssi registers.

http://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf 

Best regards
igor

0 Kudos

1,081 Views
marksatterfield
Contributor I

Here are some of the SSI register values before I enable xmit and after.

544539 PID:400002 TID:4e901ee StartSsi: STCCR before xmit = 0x1610b
544540 PID:400002 TID:4e901ee StartSsi: SFCSR before xmit = 0xf880f88
544540 PID:400002 TID:4e901ee StartSsi: SCR before xmit = 0x131
544540 PID:400002 TID:4e901ee StartSsi: STCR before xmit = 0x3ef
544540 PID:400002 TID:4e901ee StartSsi: SISR before xmit = 0x0
544541 PID:400002 TID:4e901ee StartSsi: SIER before xmit = 0x0
544541 PID:400002 TID:4e901ee StartSsi: SFCSR before xmit = 0xf880f88
544541 PID:400002 TID:4e901ee StartSsi: SISR after xmit = 0x0
544541 PID:400002 TID:4e901ee StartSsi: SCR after xmit = 0x133

The target is running WEC7.

Here are the initial values for some of the SSI and Aud Mux registers:

2996 PID:400002 TID:ab002e InitSsi: STCCR = 0x1610b
2996 PID:400002 TID:ab002e InitSsi: SFCSR = 0x880088
2996 PID:400002 TID:ab002e InitSsi: SCR = 0x130
2996 PID:400002 TID:ab002e InitSsi: STCR = 0x26f
2997 PID:400002 TID:ab002e InitSsi: SIER = 0x0
2997 PID:400002 TID:ab002e InitSsi: SISR = 0x3003
2997 PID:400002 TID:ab002e InitAudmux: PTCR2 = 0x800
2997 PID:400002 TID:ab002e InitAudmux: PDCR2 = 0x4000
2998 PID:400002 TID:ab002e InitAudmux: PTCR3 = 0x8c400800
2998 PID:400002 TID:ab002e InitAudmux: PDCR3 = 0x2000

0 Kudos