Hello NXP community,
I am completely new here to this community and also to NXP microcontrollers. In the past I was working with many microcontrollers made by other manufacturers. Now our company is going for i.MX8Mini and my job will be to develop firmware for the Cortex M4F in it. Unfortunately I can't find very much information on this, neither on the hardware side nor the software side. Thats why I come here with a number of questions:
- Where does the cortex M4F core get its program from? There seems to be no flash, only TCM. How is that loaded?
- Is a start of the cortex M4 after power up possible without starting the cortex A53?
- How is either of the cores accessing peripherals while assuring that there will be no collisions? Can one core block a peripheral for all other cores or something like that?
- How do the A53 and M4 core communicate with each other? Which are the limitations of the communication interfaces (throughput, buffer sizes...)
- Is there an IDE ideally GCC based for the Cortex M4 with some example projects to start from?
- How do I upload a program from IDE to cortex M4 and test it totaly independant of the A53 cores?
- Which debugging options do I have? Is there SWD or JTAG? Which external tools do I need? Are they supported by the named IDE?
Our goal is to use the M4 core for low power and basic functionality and use A53 cores only when their computing power is needed. So there are basically two independent applications on M4 and A53 cores.
Thanks a lot for any help
Hello Radhika Somaiya,
thank you for your help, it is very valuable.
From the Getting Started with MCUXpresso SDK for EVK-MIMX8MM.pdf doc I would read that as a link between JTAG and PC a Segger J-Link is needed. Can you confirm that?
Thanks for further information
Is a start of the cortex M4 after power up possible without starting the cortex A53?
- Cortex A53 is responsible for enabling Cortex-M4.
From section 1.6 of i.MX8M Mini Applications Processor Reference Manual :
The chip will always boot from A53 core first, the M4 core will be held in reset during the A53 boot and won’t run until it is enabled by the A53 core. The image for M4 cores will be loaded into memory and authenticated by the A53 core.
How is either of the cores accessing peripherals while assuring that there will be no collisions? Can one core block a peripheral for all other cores or something like that?
- Basically all the peripherals could be handled by either the Cortex-A or Cortex-M cores.The Resource Domain Controller (RDC) provides support for the isolation of destination memory mapped locations such as peripherals and memory to a single core.
How do the A53 and M4 core communicate with each other? Which are the limitations of the communication interfaces (throughput, buffer sizes...)
- For communication between cores:
Steps to run rpmsg on i.MX8M mini : Where is the RPMsg document for IMX8MM?
For building an application you can follow the steps from Getting Started with MCUXpresso SDK for EVK-MIMX8MM.pdf (from docs folder of Downloded SDK).
We are looking for solution of remaining questions.
meanwhile I found some answers myself:
- IDE is MCUxpresso
- there is only JTAG on i.MX8 and only one for all cores
Still need some information or information sources for the other questions.
NXP team please help
Thank you very much