Native chip-select support on spi-fsl-lpspi.c

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Native chip-select support on spi-fsl-lpspi.c

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Contributor V

Hi,


I'm using the 4.14.98 GA BSP where I need to use native chip-select (i.e. dedicated SPI chip-select pin instead of GPIO chip-select) for one of our device.

I have gone through the "spi-fsl-lpspi.c" file where they include "<linux/spi/spi_bitbang.h>" but, not specifically used anything directly from the "spi_bitbang" (as far as I understand).

However, the driver still using the "cs-gpios" for chip-select in the probe function.

Hence, I would like to know whether the 4.14.98 GA BSP's spi-fsl-lpspi.c supports native chip-select? I do not have any dedicated GPIO pin for the chip-select and need to use the SPI native chip-select pin for the same.

Could anyone please confirm that, the driver is capable to handle the native chip-select pin instead of a GPIO chip-select pin?

Looking forward to your reply.

Thank you in advance,
Ajith P V

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NXP TechSupport
NXP TechSupport

In this 7ulp dts example, pinctrl-0 is refer to "default", pinctrl-1 is refer to "sleep". In our case, I think you don't need to add the "pinctrl-1" and "sleep" in your device tree file.

The 0x0 value is the PAD Ctrl setting of the pins.

I think you can refer to this one.

fsl-imx8qxp-lpddr4-arm2-lpspi.dts\freescale\dts\boot\arm64\arch - linux-imx - i.MX Linux kernel 

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NXP TechSupport
NXP TechSupport

Basically, you don't need an extra pin for cs-gpio. You just need to change the IOMUX setting for the SPI's CS pin to GPIO pin.

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Contributor V

Thank you for your reply. I was configuring the IOMUX setting for the SPI's CS pin to GPIO pin earlier, in other projects.

The pin currently I'm using do not have GPIO option under IOMUX, however have native SPI CS option (along with other options).

Hence, I asked this question.

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NXP TechSupport
NXP TechSupport

which i.MX chip are you using?

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Contributor V

Could you please let me know whether the 'spi-fsl-lpspi.c' driver have native chip-select support?

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NXP TechSupport
NXP TechSupport

yes, supported.

you can take this for reference.

imx7ulp-evk.dts\dts\boot\arm\arch - linux-imx - i.MX Linux kernel 

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Contributor V

Thank you very much jimmychan‌ for providing the reference link.


I can see the configuration from the link for native CS as below:

&lpspi3 {
    #address-cells = <1>;
    #size-cells = <0>;
    fsl,spi-num-chipselects = <1>;
    pinctrl-names = "default", "sleep";
    pinctrl-0 = <&pinctrl_lpspi3>;
    pinctrl-1 = <&pinctrl_lpspi3>;
    status = "okay";

    spidev0: spi@0 {
        reg = <0>;
        compatible = "rohm,dh2228fv";
        spi-max-frequency = <1000000>;
    };
};

pinctrl_lpspi3: lpspi3grp {
            fsl,pins = <
                IMX7ULP_PAD_PTF16__LPSPI3_SIN    0x0
                IMX7ULP_PAD_PTF17__LPSPI3_SOUT    0x0
                IMX7ULP_PAD_PTF18__LPSPI3_SCK    0x0
                IMX7ULP_PAD_PTF19__LPSPI3_PCS0    0x0
            >;
        };

However, not clear on the below points:

  1. Is there any reason w.r.t native CS for adding "sleep" apart from the "default" with "pinctrl-names"?
  2. Why there is one more entry as "pinctrl-1 = <&pinctrl_lpspi3>;" in the configuration with the same "pinctrl_lpspi3" pins?
  3. Is there any reason w.r.t native CS for making all the IOMUX pin value as 0x0 inside "lpspi3grp"


Could you please give some insight on the above queries?

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NXP TechSupport
NXP TechSupport

In this 7ulp dts example, pinctrl-0 is refer to "default", pinctrl-1 is refer to "sleep". In our case, I think you don't need to add the "pinctrl-1" and "sleep" in your device tree file.

The 0x0 value is the PAD Ctrl setting of the pins.

I think you can refer to this one.

fsl-imx8qxp-lpddr4-arm2-lpspi.dts\freescale\dts\boot\arm64\arch - linux-imx - i.MX Linux kernel 

View solution in original post

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Contributor V

Thank you very much jimmychan‌ for your wonderful support!

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Contributor V

I'm using i.MX8 chip and the platform is a custom one.

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