My LVDS Display is buggy. please help [Video attached]

[jacoblindberg]

Hello,

I am using an IMX8MN with Linux Yocto to control a 4 channel LVDS display. I finally, after many hours of diagnosing, was able to get the screen resolution to be what it should be. The issue im having now is that the screen is a little buggy, and I know that I have to fix something in the respective code snippet to control the LVDS display in the device tree, but I dont know what. I have attached a video below so that you can all see the issue im having. I have also attached the picture of the code snippet that I had to change from the default device tree, and Im wondering if I need to change any of the parameters in here to get it to not be buggy. The screen that I am using is this one. it runs the VESA data protocol with RGB888. It has 4 lanes and the dsi to lvds bridge that I am using is the sn65dsi83 texas instrument chip. The hardware SOM we are using are varisicite som nanos with the IMX8MN processor. 

The dsi-lanes can be any integer from 1 to 4, and i dont know if I should change this to 4 because there are 4 data lanes going to the screen? Right now it is 1. I just dont know what could be the source of the bugginess issue. Any help from this kind community would be greatly appreciated.

thank you!

[Zhiming_Liu]

Hi @jacoblindberg 

Do you have the timing information about this screen?

1.Please check the timing of this screen.

2.Check the pixel clock in sn65dsi83

[jacoblindberg]

hello @Zhiming_Liu 

Yes I have tested them and written the proper information into the right place. We get a solid screen now with no buggy issues, but sometimes it does bug on and off and it seems like a ghost issue that only apears every once and a while. I have attached the datasheet of our screen as well as the code for the timing nodes in the device tree I have set for the screen. Let me know if you see anything strange. 

dsi_lvds_bridge: sn65dsi84@2c {
compatible = "ti,sn65dsi83"; /* done */
reg = <0x2c>; /* done */
ti,dsi-lanes = <1>; /* done, keep at 1 */
ti,lvds-format = <2>; /* done, format 1 <1> must be selected when RGB888(24bpp) data is received from DSI */
ti,lvds-bpp = <24>; /* done, 24 bits of data each lane */
ti,lvds-channels = <1>; /* done, one main channel */
ti,width-mm = <108>; /* done, pixel active area width */
ti,height-mm = <65>; /* done, pixel active area height */
enable-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* done, dont touch this */
pinctrl-names = "default"; /* done */
pinctrl-0 = <&pinctrl_lvds>; /* done */
status = "okay"; /* done, put "disable" if you want to disable... but we do not */
display-timings {
lvds {
clock-frequency = <25000000>; /* done, changed from 33MHz to 25MHz */
hactive = <800>; /* done, unchanged pixel height */
vactive = <480>; /* done, unchanged pixel height */
hback-porch = <8>; /* done, changed hback from 40 to 8 */
hfront-porch = <8>; /* done, changed hfront from 40 to 8 */
vback-porch = <8>; /* done, changed vback from 29 to 8 */
vfront-porch = <8>; /* done, changed vfront from 13 to 8 */
hsync-len = <4>; /* done, changed hsync from 48 to 4. Related to pulse width */
vsync-len = <4>; /* done, changed vsync from 3 to 4. Related to pulse width */
hsync-active = <0>; /* done, unchanged but may need to test */
vsync-active = <0>; /* done, unchanged but may need to test */
de-active = <1>; /* done, unchanged but may need to test */
pixelclk-active = <0>; /* done, unchanged but may need to test */
};
};
port {
dsi_lvds_bridge_in: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
};
};

Thank you

[Zhiming_Liu]

If you configure the correct the pixel clk and timing, this unstable issue may caused by sn65dsi83 hardware

[jacoblindberg]

I tested ti, dsi-lanes = <4> and it made it worse. This is not the fix I repeat:(

Still cant get the goodix gt711 touchscreen to work on the screen either...