Multicore question regarding the IMX1170...

[EdSutter]

My application (currently working with MIMXRT1170EVKB and SDK_25_03_00) may eventually require that both the M7 and M4 cores be able to access (instruction and/or data) portions of memory that will be in FLEXSPI-Serial-NOR-Flash.  The reason is simply that both cores may have more text/data/bss than there is internal RAM space.  So I wanna make sure I know what I'm up against, here's my question...

It is 100% up to the two cores to coordinate this correct?  In other words there is no arbitration hardware on this SOC for any area of external memory (be it FlexSPI-NOR or SDRAM) that allows both cores to access the same memory block...

True?

[mayliu1 · Accepted solution]

Hi @EdSutter ,

Thank you so much for your interest in our products and for using our community.

Yes, your understanding is correct.

There is no arbitration hardware on this SOC for any area of external memory (be it FlexSPI-NOR or SDRAM) that allows both cores to access the same memory block.

The two cores must explicitly coordinate accesses to external memory through software-based synchronization.

Wish it helps you. 

Wish you a nice day!

Best Regards
MayLiu