Modification of some connections PMIC-SABRE SDB

[EgleTeam]

Hi,

Looking the schematics of the SABRE SDB we have few doubts about the posibility of making few modifications of the PMIC configuration (sheet 19) for a custom design.

1. Can we remove the SWBST input switching circuit (Q510+Q511)?. We can't find any reference to "SWBST_PWR_EN" on the rest of the schematics so we assume that SWBST is always ON due the pull-up (R592).

2. Can we left unconnected LICELL pin if we don't plan to use the RTC when the iMX6 is off?.

3. We want to use the "F0" pre-programmed configuration (which seems to be the same used in SABRE SDB although the PMIC is a "NP" part). Is safe to remove all shorts/jumpers? Since the design is already tested....

4. What purpose is "PWR_BTN_SNS"? Can we remove this connection and D4 if "AUTO ON" is used?.

Best regards,

Manuel

[JorgeRama_rezRi · Accepted solution]

Hi Manuel,

1. The purpose of Q510 and Q511 is to block main system power from the 5V SWBST circuit until sometime after the PMIC receives a turn on signal. Without the power isolation FET (Q511), system 4.2V power will always be supplied to attached 5V loads: One of which is the LVDS display. Turning on the SWBST circuit in the PMIC only turns on the circuit to boost the 4.2V signal up to 5V: It does not isolate 4.2V system power from the load.

Q510 is the control switch to the isolation FET. It is set to either allow 5V power to turn on when SW4 turns on (which allows 5V load to be completely disengaged when SW4 turns off), or to turn on with VDDSOC, which will allow 5V power to stay on even when the processor is in deep sleep mode.

These FETs are not exactly controlled by SWBST_PWR_EN but by AUX_3V15. It is recommended to leave the FET array in your schematic.

2. If you don't need the RTC when the system is off, you don't have to place a battery at the LICELL pin, but place a 0.1uF capacitor from LICELL to GND if this pin is not used.

3. You can remove all shorts and jumpers and make the connections you need directly. Please be careful with the shorts and jumpers that are open in the reference design.

4. The purpose is just to sense when the power button has been pressed. Yes, you can remove it if you don't need this feature.

Best regards.

Jorge.

[EgleTeam]

Hi Jorge,

thanks for the support.

1. We didn't know that Vout = Vin on SWBST when it is not working: we expect 0VDC like the rest of converters/regulators. In principle we plan to use SWBST only to supply USB comparators which, according to the reference manual, can be powered at any time. On any case we will leave the isolation circuit just in case.

2. Perfect.

3. Perfect!. Double check on DNP parts.

4. Perfect!.

Please, let us ask you few more questions:

A. We will place termination resistors in DRAM ADDRESS/COMMAND nets. We will use an external LDO (we prefer to keep SW4 at 3.15V). Is it important which source be used to supply the regulator? We're not sure wich one to use, SW2, SW4 or directly the main supply: we're afraid of DRAM be initialized before SW2 or SW4 be stable.

B. We are a bit confused regarding the procedure for turn on/turn off and reset PMIC & SoC:

B1. ONOFF SoC pin is for turn on/ turn off the PMIC. If not used (AUTO ON desired), can we leave it floating and remove PMIC_ON_REQ connection?

B2. The reference manual of the SoC(Dual/Quad)says (page 4992) that PMIC_STBY_REQ pin can power off the PMIC (in addition to take it to stand-by).We haven't found anything about it in the PMIC datasheet. Can also PMIC_STBY_REQ pin power on the PMIC or would be necessary to use ONOFF pin?.

B3. In the page 21 of the SABRE SDB schematics we found that it has been used PWRON PMIC pin as main reset (SoC is reseted by the PMIC after the switch is released). So we guess that PWRON is configured in "level sensitive mode". We assume that all common input/output reset signals (JTAG, AUDIO codecs, ETH PHY, etc.) should be connected to POR_B and not to PWRON. Am I wrong?

There are quite variables and potential situations that we don't fully understand. Thanks for your understanding.

Best regards,

Manuel.

[JorgeRama_rezRi]

Hi Manuel,

A. We used to have termination resistors in old versions of the automotive reference design to net P0V75_DDR_VTT. Let me find out why did we use this regulator and I'll get back to you with a more accurate answer.

B1. Correct, you can just leave it open for an always-on application. Please also note that the PF0100 PMIC also has a PWRON button, that one has to be pulled-up to VSNVS with a 10K resistor since it is active high when PWRON_CFG bit is 0 (please also make sure to configure this bit as 0).

B2. Yes, you can turn it off by means of the standby pin. Please see tables 30, 40 and 93 of the PMIC datasheet. You can configure the regulators to be off in standby mode with the SWxMODE, SWxxSTBY and VGENxSTBY bits.

B3. Correct, input/output reset signals should be connected to POR_B. Reset via PWRON should only be used for manual resets.

Best regards.

Jorge.

[EgleTeam]

Jorge,

All "B" questions are clear now: thank you!.

Regarding to "A": I would like to explain me better. We do not want to use PMIC SW4 at 0.75V for the termination resistors. We plan to use an external LDO powered by SW3AB (1.5V): the issue is that the control of this LDO is powered at 2.5-3.3V so we need to use another supply.

The datasheet of the PMIC (page 20) says that SW2 (3.3V) is powered up before SW3AB(1.5V). However the schematic of the SABRE SDB says the oposite. On the first case we won't have any problem. On the second case the DRAM would be powered before we could turn on the VTT regulator. Not sure if this case would cause a fail on the DDR3 or not.

Best Regards,

Manuel.

[EgleTeam]

Hi Jorge,

We have decided to use an external LDO to supply VSNVS at 3.0V. We will also use this LDO to supply VDDHIGH_IN (we will remove D10) and to supply the VTT regulator (we avoid the issue described above). We will leave VSNVS LDO of the PMIC floating and connected to their correspondent capacitor. Please comment if you find something wrong.

For finish: Would you be so kind as for explain us what happens with NVCC_PLL_OUT?. Both SABRE SDB (page 20) and SABRE AI (page 21) schematics show that in some moment an LDO has been used  to supply this pin. SABRE SDB says that is posible to use an LDO to supply this pin and SABRE AI says that the LDO is no longer needed because the problem has been fixed on the MX6. It seems like this internal LDO (NVCC_PLL_OUT) was broken in some silicon revision and it has been used an external LDO tied to this pin but we can't find any reference on the Chip Errata and the Hardware development guide.

Best regards,

Manuel.

[JorgeRama_rezRi]

Hi Manuel,

About the termination resistors: Using an external regulators is fine and seems to be the best solution if you are using SW4 for other purpose. Please take into account the following (from your description, seems like these points are already covered):

   - Termination voltage must be ½ DDR supply voltage, as you know. And it must track it.

   - The termination voltage must not turn on before DDR supply is on.

   - The termination supply must be able to sink and source current.

   - Resistor value should match trace impedance. Trace on our boards = 50 ohms.

About SW2 turning on before SW3: The power-up sequence of the PMIC regulators if fully flexible and can be programmed according to your needs. In the PMIC datasheet, the power up sequence shown is the default one. In the SABRE SDB, we programmed it for SW3 to turn on before SW2. You can do the same for your application, you just need to order your specific power-up sequence and we'll program the PMICs for you, or you can do it manually too.

About NVCC_PLL_OUT: Yes, version 1.0 of silicon had an issue with this regulator, but it was fixed in 1.1. The version that's currently being sold is 1.2, so if you are about to purchase your processors, you won't have any problem with this. This issue is not in the errata because it has already been fixed.

I guess this answer all your questions. Please let me know if I missed any or if you need anything else.

Best regards.

Jorge.

[JorgeRama_rezRi]

Just noticed I was missing one thing. About your statement:

"We have decided to use an external LDO to supply VSNVS at 3.0V. We will also use this LDO to supply VDDHIGH_IN (we will remove D10) and to supply the VTT regulator".

I'd recommend the VTT regulator to be supplied by the same regulator that's supplying the DDRs (SW3) for the VTT voltage to track it. Please make sure the regulator you choose for VTT has this specific capability.

Best regards.

Jorge.

[EgleTeam]

Hi Jorge,

Thanks for the clarifications.

Regarding NVCC_PLL_OUT: perfect!. We haven't bought SoCs yet so we will not install an additional LDO.

Regarding to the termination resistors: We keep in mind your recomendations. The regulator will be the following one:

http://www.ti.com/lit/ds/symlink/tps51200.pdf

The regulator has 2 voltage sources: one for the control ( VIN = 2.5V to 3.3V) and other for the LDO that generates VTT (VLDO = 1.1V to 3.3V). It also has REFOUT and a ENVTT control signal to enable the VTT output. (please see page 6).

IN PRINCIPLE if we supply VIN & ENVTT with the same LDO that we supply VSNVS & VDDHIGH_IN (first rail powered up in the board), the VTT output will be enabled before DDR is powered but the output will be 0V because VLDO is 0V (not powered yet by PF0100). Once PF0100  turn on  the 1.5V converter the output in the VTT regulator will be at 0.75V in very few time. Also we won't use the REFOUT output of the regulator (which is enabled although VTTEN is OFF), but the REFOUT of PF0100: so, DDR reference voltage won't be enabled before 1.5V be available.

On any case if you recommend us we can install an auxiliary circuit to switch ENVTT at the same time than PF0100 turns on 1.5V: in this case the termination resistors would be floating instead of at 0V before DDR be powered.

Best regards,

Manuel.