Mismatch between TIMING_CFG_2 and MR2

[jekim]

Hello,

I generated lpddr4x_timing.c file with configtool for imx93evk. I found the RD_TO_PRE of TIMING_CFG_2 is not matched with the nRTP of lpddr4x MR2. RD_TO_PRE is 15 and nRTP of MR2 is 14. What's the reason of this mismatch made by the configtool? 

If the RD_TO_PRE is longer than the actual memory nRTP(auto precharge timing), do following commands also have the delay of one cycle?

Does RD_TO_PRE parameter have the same effect on both lpddr4x and lpddr4?

Thanks.

[pengyong_zhang · Accepted solution]

hi @jekim 

Can I expect the future Configtool will match RD_TO_PRE with MR2 nRTP like the earlier v15? 

>>>Sure, i will contact our internal Config Tool talk about this request, Maybe they will fix it on the next version. also thanks for your feedback abou this.

B.R

[pengyong_zhang]

HI @jekim 

What do you mean the engineering sample?

I see, So i can not reproduce your error, also we have never meet this qquestion on our i.MX93 EVK board before. So i think its hard to find the root cause because i do not clear about your test.

B.R

[jekim]

Hi @pengyong_zhang ,

Engineering sample is not from the standard manufacturing process. So, it could have better or worse performance per its experiment content. 

Can I expect the future Configtool will match RD_TO_PRE with MR2 nRTP like the earlier v15? 

Thanks.

[pengyong_zhang]

Hi @jekim 

Actually, I still do not understand your testing process, Could you tell me more details the each test and the test result?

Because, in my site, I can not reproduce your error on my i.MX93 EVK board.

B.R

[jekim]

Hi @pengyong_zhang ,

As I mentioned before, it is an engineering sample. It's not easy to see it from your side.

Thanks.

[pengyong_zhang]

Hi @jekim 

Please use our latest Config Tool v16.1 and test again.

https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-developm...

B.R

[jekim]

Hi @pengyong_zhang ,

The latest V16.1 also shows mismatch between RD_TO_PRE(15) and MR2 nRTP(14).

The old V15 showed matched value between RD_TO_PRE(14) and MR2 nRTP(14).

Thanks.

[pengyong_zhang]

HI @jekim 

What is your mem test code? And what is your failed log ? Because, in our i.MX93 EVK board we have not found any error when we run the memtester. 

B.R

[jekim]

Hi @pengyong_zhang ,

I saw the failure from an engineering sample. So, it wouldn't be seen easily from everywhere. The failure log showed different single bits every time. btw, the mismatch happens from the configtool v16. where can I  see the change history?

Thanks.

[pengyong_zhang]

HI @jekim 

You are right. So it is strange at RD_TO_PRE 15, your memtester is failed. Could you please tell me more details about your test？Include test command and each test steps, maybe i can try reproduce your case on my site.

PS : you are using our NXP i.mx93 EVK board? 

B.R

[jekim]

Hi @pengyong_zhang ,

Yes. I'm using the NXP iMX93 EVK with the public memtester software.

memtester version 4

Thanks.

[pengyong_zhang]

Hi @jekim 

When RD_TO_PRE changes from 14 to 15, the DDRC will be delayed by one or two clock cycles after the DRAM is precharge.

B.R

[jekim]

Hi @pengyong_zhang ,

If every following memory accesses were delayed evenly from the expected precharge, it has no reason to make the sample failed at RD_TO_PRE 15 while pass at RD_TO_PRE 14. I assume the following active command is delayed but the following read command is not delayed.

Thanks.

[pengyong_zhang]

HI @jekim 

There is no different about RD_TO_PRE definition between LPDDR4 and LPDDR4X, It is the RM error, i have told the DDR internal team, I think they will fix it in the next RM version.

B.R

[jekim]

Hi @pengyong_zhang ,

Thank you for the clarification. The ConfigTool sets MR2 nRTP 12 and RD_TO_PRE 15 at the slower speed 1600MHz. The lpddr4x sample is not failing at the slower speed. I want to know what happens when RD_TO_PRE is 15 at 1866MHz. Could you let me know how the memory access is changed when the RD_TO_PRE is changed from 14 to 15?

Thanks.

[pengyong_zhang]

HI @jekim 

Please lower the DDR frequency and try RD_TO_PRE 15  again.

B.R

[jekim]

Hi @pengyong_zhang ,

I will try it but could you please answer about the different RD_TO_PRE definition between LPDDR4 and LPDDR4X?

Thanks.

[pengyong_zhang]

HI @jekim 

As I mentioned before, I saw one failing lpddr4x sample with RD_TO_PRE 15

>>> Could you please tell more about this fail LPDDR4X sample? What test did you run or anything other situation?

Does same RD_TO_PRE setting make the different effect on LPDDR4 and LPDDR4X?

>>> As i know, LPDDR4 and LPDDR4X only the VDDQ is different, So i think same RD_TO_PRE setting make no different effect on LPDDR4 and LPDDR4X.

B.R

[jekim]

Hi @pengyong_zhang ,

As I mentioned before, I saw one failing lpddr4x sample with RD_TO_PRE 15

>>> Could you please tell more about this fail LPDDR4X sample? What test did you run or anything other situation?

<<< the lpddr4x sample was failed with memtester.

Does same RD_TO_PRE setting make the different effect on LPDDR4 and LPDDR4X?

>>> As i know, LPDDR4 and LPDDR4X only the VDDQ is different, So i think same RD_TO_PRE setting make no different effect on LPDDR4 and LPDDR4X.

<<< then, what's the reason of the imx93 reference manual shows different definition between LPDDR4 and LPDDR4x?

Thanks.

[pengyong_zhang]

Hi @jekim 

Thanks for your picture, i have talked with our DRAM internal team, This is because our DDRC IP error, it can not be set 14, So we use the 15 value, Although it does not match the value of the MR2 register, it does not significantly affect the performance of DDR.

B.R