Minimum interval i.MX6 read -> write and write -> read cycle.

[satoshishimoda]

Hi community,

I have a question about i.MX6 some interface.

Please see the attached file.

If user repeat read -> write -> read -> write -> ... on the following interfaces, could you let me know the minimum interval between read -> write and write -> read?

GPMI (NAND Fhash)

USB

uSDHC (SD card)

Best Regards,

Satoshi Shimoda

[igorpadykov · Accepted solution]

Hi Satoshi

I am afraid it is not possible to answer on that since

internal delays are impossible to predict or calculate.

For example with 8-8-8 DDR and tRALAT =5 one can have

about 50ns @532 MHz just for accessing data from memory.

Latencies caused by OS can be found below

LMbench Benchmarks on i.MX.

Best regards

igor

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