Minimal resolution on LVDS, iMX6S

[cerma]

Hello, what is minimal resolution on LVDS? I saw in datasheet that minimal frequency is 0 - 85 MHz but there was also mentioned that minimal frequency is 25 MHz. I need to set 480x272 (frequency about 9 MHz) but I don't know if is that even possible. Is it possible to set this resolution, if so, how?

[weidong_sun · Accepted solution]

Hello Jaroslav,

     9MHz should be no problem, one of our customers set (320X240) 6.4MHz with LVDS1 port successfully, please refer to the following steps and adjust your source code :

(1)ldb.c ( configuring your LCD's timg according to LCD's datasheet)

static struct fb_videomode ldb_modedb[] = {
{
"LDB-XGA", 60, 320, 240, 155914,
38, 20,
15, 4,
30, 3,
0,
FB_VMODE_NONINTERLACED,
FB_MODE_IS_DETAILED,},

(2)Adjusting clock source code in /arch/arm/mach-mx6/clock.c

Find :

clk_set_parent(&ldb_di0_clk, &pll2_pfd_352M);

       clk_set_parent(&ldb_di1_clk, &pll2_pfd_352M);

and change it to be:

clk_set_parent(&ldb_di0_clk, &pll5_video_main_clk,);

       clk_set_parent(&ldb_di1_clk, &pll5_video_main_clk,);

(3)BSP file: mach-mx6q/board-mx6q_sasbresd.c

static struct ipuv3_fb_platform_data sabresd_fb_data[] = {

            { /*fb0*/

            .disp_dev = "ldb",

            .interface_pix_fmt = IPU_PIX_FMT_RGB666,

            .mode_str = "LDB-XGA",

            .default_bpp = 16,

            .int_clk = false,

            .late_init = false,

"int_clk = false" means the clock source is from PLL2_PFD_352 or pll5_video_main_clk  ; "int_clk = true" means clock source is from IPU(264MHz)

Hope the above advice can help you !

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If above suggestion can help you resolve your issue, please help close the post !

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Regards,

Weidong

[haitao]

你好，weidong!

按照你的方法，我得到的时钟最低为25.6M，我得不到9M的时钟。不知道为什么