Micron MT41K128M16JT-125:K with iMX6SX

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Micron MT41K128M16JT-125:K with iMX6SX

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1,870 次查看
robyf
Contributor IV

Hi All,

we have developed a custom board where we have used a DDR3 Micron MT41K128M16JT-125:K, but we are not able to configure it because the DDR3 script aid seems not updated for iMX6SX CPU.

The DDR stress tool pass correctly after a run of 12h. Does anyone can help to setup correctly the corresponding DCD?

Thanks in advance,

Roberto Fichera.

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1 解答
1,072 次查看
robyf
Contributor IV

I've sorted out the problem by using u-boot-imx instead of FSL.

在原帖中查看解决方案

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1,072 次查看
gusarambula
NXP TechSupport
NXP TechSupport

I’ll ask if there are plans for the Script Aid to be updated for the i.MX6SX. In the meantime perhaps you may find useful to start from the parameters used by our BSP Release for the i.MX6SX SDB. The i.MX6SX SDB uses the MT41K256M16HA but it might help as a starting point.

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1,072 次查看
robyf
Contributor IV

Hi Gusarambula,

yes! that board was my starting point, so the sabresd with iMX6SX. Currently I'm getting printed out only board info and then uboot stops just afterwards.

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1,073 次查看
robyf
Contributor IV

I've sorted out the problem by using u-boot-imx instead of FSL.

1,072 次查看
mchaplet
Contributor II

Hi Roberto,

I'm developing a board with exactly the same combination (IMX6SX - MT41K128).

Finally, did you modified DCD part ?

I guess you modified MMDC_MDASP (0x021b0040) for size (8Gb -> 2Gb) and MMDC_MDCTL (0x021B0000) for bus size (64-> 16bits) but did you modified MR commands or calibration settings ?

Can you just share your imximage.cfg file (used to build U-Boot imx image) ?

Thanks for your help,

Martin

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1,072 次查看
robyf
Contributor IV

Hi Martin,

yes I've modified the DCD part. My PCB has 2xDDR3 so it's a 512MB memory space with single CS

My MMDC_MDASP for single CS is DATA 4 0x021b0040 0x0000004f    // CS0_END - 0x9fffffff (512MB)

and MMDC_MDCTL is DATA 4 0x021b0000 0x83190000    // MMDC0_MDCTL - row - 14bits; col = 10bits; burst length 8; 32-bit data bus

You should also collect all DDR3 calibration values and put them in the proper register

Here is my current DCD, I hope it helps.

Cheers,

Roberto Fichera.

/*

* Copyright (C) 2014 Freescale Semiconductor, Inc.

*

* SPDX-License-Identifier: GPL-2.0+

*

* Refer docs/README.imxmage for more details about how-to configure

* and create imximage boot image

*

* The syntax is taken as close as possible with the kwbimage

*/

#define __ASSEMBLY__

#include <config.h>

/* image version */

IMAGE_VERSION 2

/*

* Boot Device : one of

* spi/sd/nand/onenand, qspi/nor

*/

#ifdef CONFIG_SYS_BOOT_QSPI

BOOT_FROM qspi

#else

BOOT_FROM sd

#endif

#ifdef CONFIG_SECURE_BOOT

CSF 0x2000

#endif

/*

* Device Configuration Data (DCD)

*

* Each entry must have the format:

* Addr-type           Address        Value

*

* where:

* Addr-type register length (1,2 or 4 bytes)

* Address   absolute address of the register

* value   value to be stored in the register

*/

/* Enable all clocks */

DATA 4 0x020c4068 0xffffffff

DATA 4 0x020c406c 0xffffffff

DATA 4 0x020c4070 0xffffffff

DATA 4 0x020c4074 0xffffffff

DATA 4 0x020c4078 0xffffffff

DATA 4 0x020c407c 0xffffffff

DATA 4 0x020c4080 0xffffffff

DATA 4 0x020c4084 0xffffffff /* What is this ? */

DATA 4 0x020C4018 0x00260324 /* DDR clk to 400MHz */

/* IOMUX */

/* DDR IO TYPE */

DATA 4 0x020e0618 0x000c0000  /* DDR3 */

DATA 4 0x020e05fc 0x00000000

/* CLOCK */

DATA 4 0x020e032c 0x00000030

/* ADDRESS */

DATA 4 0x020e0300 0x00000020

DATA 4 0x020e02fc 0x00000020

DATA 4 0x020e05f4 0x00000020

/* CONTROL */

DATA 4 0x020e0340 0x00000020

DATA 4 0x020e0320 0x00000000

DATA 4 0x020e0310 0x00000020

DATA 4 0x020e0314 0x00000020

DATA 4 0x020e0614 0x00000020

/* DATA STROBE */

DATA 4 0x020e05f8 0x00020000

DATA 4 0x020e0330 0x00000028

DATA 4 0x020e0334 0x00000028

DATA 4 0x020e0338 0x00000028

DATA 4 0x020e033c 0x00000028

/* DATA */

DATA 4 0x020e0608 0x00020000  /* DDR3 Input: differential */

DATA 4 0x020e060c 0x00000028

DATA 4 0x020e0610 0x00000028

DATA 4 0x020e061c 0x00000028

DATA 4 0x020e0620 0x00000028

DATA 4 0x020e02ec 0x00000028

DATA 4 0x020e02f0 0x00000028

DATA 4 0x020e02f4 0x00000028

DATA 4 0x020e02f8 0x00000028

/* Calibrations */

/* ZQ */

DATA 4 0x021b0800 0xa1390003

/* write leveling */

DATA 4 0x021b080c 0x0021001e // MMDC_MPWLDECTRL0 ch0

DATA 4 0x021b0810 0x001F001e // MMDC_MPWLDECTRL1 ch0

/* DQS Read Gate */

DATA 4 0x021b083c 0x413c013c // MMDC0 MPDGCTRL0

DATA 4 0x021b0840 0x01300124 // MMDC0 MPDGCTRL1

/* Read/Write Delay */

DATA 4 0x021b0848 0x42424042 // MPRDDLCTL PHY0

DATA 4 0x021b0850 0x36363832 // MPWRDLCTL PHY0

//DATA 4 0x021b08c0 0x2492244a /* Change duty cycle byte1 and byte2 */

/* read data bit delay */

DATA 4 0x021b081c 0x33333333

DATA 4 0x021b0820 0x33333333

DATA 4 0x021b0824 0x33333333

DATA 4 0x021b0828 0x33333333

/* Complete calibration by forced measurement */

DATA 4 0x021b08b8 0x00000800

/* MMDC init */

/* in DDR3, 32-bit mode, only MMDC0 is initiated */

DATA 4 0x021b0004 0x0002002d

DATA 4 0x021b0008 0x00333030

DATA 4 0x021b000c 0x676b52f3

DATA 4 0x021b0010 0xb66d8b63

DATA 4 0x021b0014 0x01ff00db

DATA 4 0x021b0018 0x00011740

DATA 4 0x021b001c 0x00008000

DATA 4 0x021b002c 0x000026d2

DATA 4 0x021b0030 0x006b1023    // MMDC0_MDOR - tXPR - 69ck

DATA 4 0x021b0040 0x0000004f    // CS0_END - 0x9fffffff (512MB)

DATA 4 0x021b0000 0x83190000    // MMDC0_MDCTL - row - 14bits; col = 10bits; burst length 8; 32-bit data bus

/* Initialize MT41K128M16HA-125 */

/* MR2 */

DATA 4 0x021b001c 0x04008032

/* MR3 */

DATA 4 0x021b001c 0x00008033

/* MR1 */

DATA 4 0x021b001c 0x00048031

/* MR0 */

DATA 4 0x021b001c 0x05208030

/* DDR device ZQ calibration */

DATA 4 0x021b001c 0x04008040

/* final DDR setup, before operation start */

DATA 4 0x021b0020 0x00000800

DATA 4 0x021b0818 0x00011117

DATA 4 0x021b001c 0x00000000

1,072 次查看
mchaplet
Contributor II

Thanks Roberto,

I'm still waiting for the prototype but it seems perfect.

Using a diff with original config directly show which registers need to be tuned.

Thanks again,

Martin

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