Memory range of DDR Stress Test

[ko-hey]

Hi all,

I have a question about i.MX 6/7 DDR Stress Test Tool .

I would like to know the memory range of the test.

Does it test the whole DDR memory range ?

If not, which range does it test ?

Ko-hey

[Yuri]

Hello,

  The stress test is a program, running on PC side, which downloads a test
image to the i.MX series processor’s IRAM (internal memory) through USB connection.

  So, all DRAM memory, which is preliminary initialized, using corresponding script, 
is available for testing.

Regards,

Yuri.

[ko-hey]

Hi Yuri,

Thank you for reply.

Could you tell me more detail of following answer ?

> So, all DRAM memory, which is preliminary initialized, using corresponding script, is available for testing.

Q1.

Could you tell me the meaning of "all DRAM memory” ?

Does it test for all memory space ?

Q2.

You said it's available for testing.

Does it do the test whole memory space by default ?

Q3.

When Q2 is no, can we change the setting through the options which you prepared ?

Ko-hey

[Yuri]

Hello,

  before testing, memory controller should be initialized with init script help.

Such initialization configures some memory size, depending on row, column, etc ...

parameters. Usually all available in system DRAM memory is expected for using.  

  The memory test reads the memory controller configuration and defines available

DRAM size automatically.

Regards,

Yuri.

[ko-hey]

Hi Yuri,

The init script that you said is an attachment, isn't it ?

Could you tell me which line is for initialization configures some memory size, depending on row, column ?

I guess that it's the ROW and COL field in MMDC0_MDCTL register.

Am I correct ?

Ko-hey

[Yuri]

Hello,

   The init script is selected manually, say, from ../script directory of the DDR tester application.

For i.MX 6SL I see the following files in the ../script directory:

MX6SL_EVK_DDR3_1GB_64bit_v0.4.inc

MX6SL_EVK_LPDDR2_512MB_32bit_v0.9.inc

MX6Solo_ARD_DDR3_register_programming_aid_v0.2.inc
MX6Solo_SabreSD_DDR3_register_programming_aid_v0.4.inc

  The following registers in the MMDC define the DDR address space:
• MDMISC[DDR_4_BANK]—Defines either 4 or 8 banks in the DDR device
• MDCTL[DSIZ]—Defines the DDR data bus width of x16, x32 or x64
• MDMISC[BI]—Defines whether bank interleaving is on or off
• MDCTL[COL]—Defines the column size of the DDR device
• MDCTL[ROW]—Defines the row size of the DDR device

Regards,

Yuri.