I have some questions relate to memory caching in i.MX8 system. I'm working in M4 side
I understand there are two instances/modules for caching
+ MPU in M4 core
+ LMEM in M4 subsystem
Is there any relation between MPU and LMEM. Do they depend on each other?
Is it possible if i enable both MPU and LMEM?
If i configure a DDR region is non-cacheable by MPU and enable LMEM, when i access the memory in non-cacheable region, is the data in the region cached?
Solved! Go to Solution.
Hello,
LMEM provides memory controllers for tightly-coupled processor-local memories, that is - for SRAM
and caches.
It is possible to enable both MPU and LMEM.
If one configures a DDR region is non-cacheable by MPU and enable LMEM, the data in the region are not
cached, when accessing the memory in non-cacheable region.
Regards,
Yuri.
Hello,
The MPU is M4 core's part and it configures access rules to memory for the core.
The LMEM provides the needed MPU connections for checking all SRAM controller
and cacheable accesses.
Have a great day,
Yuri
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
Hi Yuri,
As my understanding from you, LMEM only checks SRAM region?
Do you have any feedback about below questions?
Is it possible if i enable both MPU and LMEM?
If i configure a DDR region is non-cacheable by MPU and enable LMEM, when i access the memory in non-cacheable region, is the data in the region cached?
Hello,
LMEM provides memory controllers for tightly-coupled processor-local memories, that is - for SRAM
and caches.
It is possible to enable both MPU and LMEM.
If one configures a DDR region is non-cacheable by MPU and enable LMEM, the data in the region are not
cached, when accessing the memory in non-cacheable region.
Regards,
Yuri.