Max transfer rate of i.MX6 PCIe RC on architectonic

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Max transfer rate of i.MX6 PCIe RC on architectonic

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massohy
Contributor II
Dear Community Member,
 
I already know that it is difficult to get logically max throughput of pci express on i.MX6 in referring to these posts IPU/PCIe throughput problem on i.MX6 and  What is the PCIe i.MX6max payload size ?.
But I think if I connect i.MX6 with high throughput end point device, then I can get more high throughput than this post i.MX6Q PCIe EP/RC Validation System.
 
I want to know how much fast data transfer I can performed with i.MX6 PCIe use as root complex.
Please tell me how to calculate max throughput on PCIe RC of i.MX6.
 
And can I get its each max throughput on both direction data transfer?
 
Best regards,
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igorpadykov
NXP Employee
NXP Employee

Hi mas

I doubt if one can get more high throughput than described on

i.MX6Q PCIe EP/RC Validation System, as solution was provided by nxp

engineering team based on internal design documentation.

>Please tell me how to calculate max throughput on PCIe RC of i.MX6.

there is no way to claculate it as  throughput depends on many other
factors, like internal processor buses loading and delays in NIC-301 arbiters.

Best regards
igor
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aivchenko
Contributor II

I have an opposite question.

Since both PCIe and Display are sitting on the same Display switch of NIC-301 what to do to limit bandwidth on PCIe to avoid flickering on LVDS interface?

Do you have a sample code/example how to do it on i.MX6SoloX?

Do you have a corrected diagram for Chapter 43 of i.MX6SoloX reference manual rev.3 marked which ports are slave, which are masters which GPV_N belong to which peripherals, etc.

I'd also welcome information of what is the range of parameters in wr_tidemark, read_qos, write_qos.

Also, please tell me whether I should change values for AQoS CR Bandwidth and Sarutation and which Master corresponds to PER_S and Display switch on the diagram

Thanks,

--Alex

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igorpadykov
NXP Employee
NXP Employee

Hi Alex

such kind of support (with tweaking NIC-301) can be provided

with extended support of NXP Professional Services | NXP 

Best regards
igor

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igorpadykov
NXP Employee
NXP Employee

Hi mas

I doubt if one can get more high throughput than described on

i.MX6Q PCIe EP/RC Validation System, as solution was provided by nxp

engineering team based on internal design documentation.

>Please tell me how to calculate max throughput on PCIe RC of i.MX6.

there is no way to claculate it as  throughput depends on many other
factors, like internal processor buses loading and delays in NIC-301 arbiters.

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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massohy
Contributor II

Hi igor,

 

I understood I cannot get higher throughput than “i.MX6Q PCIe EP/RC Validation System” and cannot calculate max throughput. But I may be got max 211MB/s throughput based on measured values.

 

Thank you for your reply.

 

Best Regards,

 

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