Max DDR Clock Length for i.MX6

[rmerkley]

As we are laying out our board, we noticed that the SABRE board reference design doesn't follow the HW Layout Guide exactly, yet still works fine (the difference between the shortest and longest address lines is ~600 mils, but the guide says to keep them +/-25 mils).  We are trying to follow the layout guide more closely than does the reference design, but are running into a conflict.

The closest we can get our address lines is about 2500 mils.  The guide says to make the clock lines the longest trace, essentially.  That would require the clock lines to also be about 2500 mils.  However, when doing "byte lane" routing, the HW Guide says to have the clock no longer than 2250 mils.

The alternative to "byte lane" routing is to route all of the signals to be the same length.  In that case, it allows for <= 3000 mils for the clock, and everything has to essentially match whatever your clock nets are.

Questions:

1. Why the discrepancy in the recommendations in the HW Guide (2250 vs 3000 mils for the clock nets)?

2. Can we actually have the clock lines be 2500 mils when doing "byte lane" routing, so that they are the longest net in the DDR block?

Thanks.

[Yuri]

  It is known, that our boards (reference designs) sometimes violate recommended rules,
since often the boards are designed before or simultaneously with rules forming.

What we can say - basically, the best approach - to use simulation technique for PCB design.

In the same time, general rules may be provided for customers to simplify their

PCB considerations, but note, for assurance such rules are very strong.

[rmerkley · Accepted solution]

We used the Byte Lane approach, matching lanes to +/-25 mils, per recommendation, then made the clock the longest net, at about 2500 mils.  Board works flawlessly.