Master clock in I2S Master mode

_andev_ · ‎04-14-2015

Hi all,

We have a custom board with iMX6D with the 3.10.53 linux kernel. We have connected the STA559 audio codec

using AUDMUX 4 for I2S interface and GPIO_0_CLKO as Master clock, like the SabreLite one. The SSI1 is configured

in master mode. When I play a 44.1KHz sound with aplay and I can see the signals in the scope:

AUD4_TXC = I2S_SCLK = 2.82240MHz = 44100Hz x 2 Channels x 32 bits is OK

AUD4_TXD = I2S_DIN is the sound data is OK

AUX4_TXFS = I2S_LRCLK clock to channel left and right is OK

GPIO_0_CLKO = SYS_MCLK = 24MHz is NOT OK!

I know the GPIO_0_CLKO is linked to the main 24MHz OSC but we need this clock to be something like

576 * fs, 128 * fs, 256 * fs, 384 * fs, 512 * fs, 768 * fs, etc... where fs = 44.1KHz. Is it possible to get, for

example, 11.2896MHz in GPIO_0_CLK0? How???

Thanks!

igorpadykov · ‎04-15-2015

Hi Anonymous

one can try to choose appropriate clock source/with divider

using IMX6DQRM 18.6.21 CCM Clock Output Source Register (CCM_CCOSR)

and Figure 18-2 Clock Tree.

Best regards

igor

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_andev_ · ‎04-15-2015

Hi Igor, thanks for the info!

I was able to do it. One thing is to know what to do and another is how to do it!

It's not obvious how to do it. I suppose it must to be a good place to do the

changes, but I'm not a Linux expert.

I've found the CLKO is linked to the 24MHz osc in clk-imx6q.c and I've

made some changes in that file, and now I have 33.868800MHz as SYS_MCLK,

useful to generate 768*fs available in the codec.

But I think that it's not a good file choice to make the changes. Is it possible to change

the clock parent, divider and the rate in another file? The best option will be the DTS file,

but is it possible? The second option will be the ASOC machine driver file, sound/soc/fsl/imx-sta559.c.

The third is arch/arm/mach-imx/mach-imx6q.c and the last one, the current, clk-imx6q.c.

What do you think?

Any code is welcome!

Regards