MX8M GPIO Input_Val Setting conflict for i2c2

[matthewmader]

Hello,

I am currently using yocto for the VAR-SOM-MX8M-MINI which uses the freescale imx8mm-var-som.dts file.  In this file, the I2C2 SDA and SCL signals are defined with an input_val of 0x400001c3.  However, referencing the  IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL register defined in the  i.MX 8M Mini Applications Processor
Reference Manual (Rev 2.8/19), only bits 0-8 are valid.  

My question is, why is bit 30 set in the DTS file?  Is there a conflict with the documentation?

[AldoG]

Hello,

This comes from the I2C binding, from the documentation available here:
https://source.codeaurora.org/external/imx/linux-imx/tree/Documentation/devicetree/bindings/i2c/i2c....

I2C_TEN_BIT_ADDRESS        (1 << 31)
I2C_OWN_SLAVE_ADDRESS        (1 << 30)

In this case would mean I2C is a 7 bit address and the I2C own slave address.

Hope this helps,

Best regards,

Aldo.

[matthewmader]

Thanks Aldo for your quick response!

Given this new information, am I still correct in thinking that the first 9-bits of this value still come from the i.MX 8M Mini Applications Processor Reference Manual as shown below?

In the future, how should I know which bits come from the reference manual, and which bits are defined by the device bindings?

[AldoG · Accepted solution]

Hello,

Sorry I made a mistake about this, I misinterpreted your question, for pad configuration you should take a look to the devicetree documentation general and chips specific:

fsl,imx-pinctrl

fsl,imx8mm-pinctrl

As per documentation (fsl,imx-pinctrl) is the following:

Bits used for CONFIG:
NO_PAD_CTL(1 << 31): indicate this pin does not need config.

SION(1 << 30): Software Input On Field.
Force the selected mux mode input path no matter of MUX_MODE functionality.
By default the input path is determined by functionality of the selected
mux mode (regular).

As for the first 9 bits, yes you're correct you may look to the Reference Manual for pad configuration.

Sorry for the confusion,

Best regards,

Aldo.