MX6Q+LPDDR2(32bit) boot issue

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MX6Q+LPDDR2(32bit) boot issue

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raymondwang
Senior Contributor I

As I mentioned in some threads, we are trying on MX6Q+LPDDR2 combined design. but make no sense why boot failure in mfg bootimage.

We use Mx6DQSDL LPDDR2 Script Aid V0.04.xlsx to generate flashheader DCD part (attached file 6q_lpddr2_32.inc). The Samsung eMCP

DS attched,too.

Our DDR config:

Single Channel 32bit

2CS, each cs is 128Mx32 (totally 1GB)

With default DSE 40ohm (SI configuration in Mx6DQSDL LPDDR2 Script Aid V0.04.xlsx ), 400MHz DDR stress test failure, but it's okay change them

to 34ohm. But with this stress pass DCD, my uboot_mfg can't boot properly (no output in default console).

Please help us!

Original Attachment has been moved to: 6q_lpddr2_32.inc.zip

Original Attachment has been moved to: mx6q_tdh_lpddr2_400_v004.inc.zip

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raymondwang
Senior Contributor I

With help of FSL FAE, now it can boot up properly. Root cause :

We can't gate/ungate 528 pfd2 (FSL's explanation).

int arch_cpu_init(void){

/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
* to make sure PFD is working right, otherwise, PFDs may
* not output clock after reset, MX6DL and MX6SL have added 396M pfd
* workaround in ROM code, as bus clock need it
*/
writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
BM_ANADIG_PFD_480_PFD2_CLKGATE |
BM_ANADIG_PFD_480_PFD1_CLKGATE |
BM_ANADIG_PFD_480_PFD0_CLKGATE,
ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |

#if defined(CONFIG_MX6Q) && !defined(CONFIG_LPDDR2)

BM_ANADIG_PFD_528_PFD2_CLKGATE |

#endif

BM_ANADIG_PFD_528_PFD1_CLKGATE |
BM_ANADIG_PFD_528_PFD0_CLKGATE,
ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);

writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
BM_ANADIG_PFD_480_PFD2_CLKGATE |
BM_ANADIG_PFD_480_PFD1_CLKGATE |
BM_ANADIG_PFD_480_PFD0_CLKGATE,
ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |

#if defined(CONFIG_MX6Q) && !defined(CONFIG_LPDDR2)

BM_ANADIG_PFD_528_PFD2_CLKGATE |

#endif

BM_ANADIG_PFD_528_PFD1_CLKGATE |
BM_ANADIG_PFD_528_PFD0_CLKGATE,
ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);

...

}

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Raymond

suggest to build just Uboot (not MFG) and try to boot it,

flash_header.S should be modified with new DCD settings.

Regarding MFG Tool, its firmware (initramfs.cpio.gz.uboot)

should be rebuilt with new DCD, please check

i.MX_6Dual6Quad_SABRE-SD_Linux_User's_Guide.pdf

sect.3.9 "Building Manufacturing Firmware".

L3.0.35_4.1.0_LINUX_DOCS

Actually you can download just modified Uboot with MFG Tool,

modifiy ucl2.xml (also one can create new Profile, check with MFG2 Tool documentation).

u-boot-mx6q-sabresd_nopad.bin is Uboot image  without offset (0x400).

Note, for USB loading one needs the same images, but without offset.

Changed "SabreSD-SD" profile:

<LIST name="SabreSD-SD" desc="USB SDP">

    <CMD state="BootStrap" type="boot" body="BootStrap" file ="u-boot-mx6q-sabresd_nopad.bin" >Loading image</CMD>

    <CMD state="BootStrap" type="jump" > Jumping to image. </CMD>

    <CMD state="Updater" type="push" body="$ echo Load Complete!">Done</CMD>

</LIST>

On Windows platform for creating Uboot image without offset, "dd"

utility may be used (http://www.chrysocome.net/dd):

dd.exe if=u-boot-mx6q-sabresd.bin of=u-boot-mx6q-sabresd_nopad.bin  bs=1024 skip=1

Best regards

chip

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raymondwang
Senior Contributor I

I also have a double check on existed mfg u-boot-mx6q-sabresd.bin. It contains first 1k padding bytes.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Raymond

you can add to DCD (and Uboot) code to set some GPIO,

then check where code hangs.

Best regards

chip

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raymondwang
Senior Contributor I

Dear Chip

   I tried to enable 1 gpio to light on a LED, seems failure . I think this means cpu did not

run there.

   BTW, I found a DCD data to enable DDR 400MHz:

   setmem /32 0x020c4018 = 0x00060324

   Is it right?

BR

RaymondWang

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Raymond

suggest to verify that GPIO module clock is not

gated in CCM registers (CCM_CCGR).

Best regards

chip

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raymondwang
Senior Contributor I

I Add the gpio code in uboot since DCD can't access gpio module directly.

I test my uboot with sabresd DDR3 config, it does work.

  Only one CCM register is set in DCD,

setmem /32 0x020c4018 = 0x00060324

I don't think it relevant to GPIO required clocks.


  I doubt DCD ccm register setting not enough to let LPDDR2 working at 400MHz. Our board

can't pass 528MHz DDR stress test.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Raymond

you can try other settings as below

iMX6DQ LPDDR2 Initialization Issue

Best regards

chip

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raymondwang
Senior Contributor I

I tried ,same behavior as before. and that init script is 533MHz, running DDR stress test will fail.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Raymond

what BSP are you using ?

What documents (if any) are you reading when

preparing images ?

Best regards

chip

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raymondwang
Senior Contributor I

my bsp is Android4.2.2-1.1.0-GA And my board design is based on SabreSD ( but using different DDR and PMIC).

Mine is LPDD2 and PMIC is PF0100F1 (specially for LPDDR2 application)

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Raymond

I would suggest to use Linux or even SDK

at bring-up phase. They are simpler, better documented,

easier for debugging.

L3.0.35_4.1.0_ER_SOURCE_BSP

i.MX 6Series Platform SDK

Best regards

chip

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raymondwang
Senior Contributor I

I rebuild sdk_unit_test_ALL.bin with replacing smart_device dcd.c to my LPDDR2.

And add it to mfg tool

<LIST name="DWLD_IN_SDP" desc="Download and execute a binary!">

    <CMD state="BootStrap"  type="find" body="Recovery" timeout="180"/>

    <CMD state="BootStrap" type="boot" body="Recovery" file="sdk_unit_test_ALL.bin">Loading

SDK image</CMD>

    <CMD state="BootStrap" type="jump">Jumping to SDK image.</CMD>

</LIST>

The mfgtool hangs with display state in "Loading SDK image" about 75% over 5mins.

I enclosed my new dcd.c.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Raymond

I would suggest to start

with attached examples. One uses iRAM,

second DDR3 - you can modify it for LPDDR2.

Optionally you can build SDK examples and run in iRAM using link below

iRAM (OCRAM) i.MX6 SDK Application

Best regards

chip

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raymondwang
Senior Contributor I

Since we doubt that MX6DQ can't switch DDR 400MHz in DCD,we replace MX6DQ to MX6DL (6dl only support 400MHz max). Now mfg uboot can boot up.

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igorpadykov
NXP TechSupport
NXP TechSupport

Probably DCD was not correct for MX6DQ.

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raymondwang
Senior Contributor I

  I don't think so since it's generated by FSL designing aiding tool. Meanwhile FSL local FAE also tried his DCD.

  FSL local FAE told me today that he will take our board to Freescale ShangHai RD center to find out root cause.

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igorpadykov
NXP TechSupport
NXP TechSupport

OK, I think it is good solution.

Best regards

chip

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raymondwang
Senior Contributor I

With help of FSL FAE, now it can boot up properly. Root cause :

We can't gate/ungate 528 pfd2 (FSL's explanation).

int arch_cpu_init(void){

/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
* to make sure PFD is working right, otherwise, PFDs may
* not output clock after reset, MX6DL and MX6SL have added 396M pfd
* workaround in ROM code, as bus clock need it
*/
writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
BM_ANADIG_PFD_480_PFD2_CLKGATE |
BM_ANADIG_PFD_480_PFD1_CLKGATE |
BM_ANADIG_PFD_480_PFD0_CLKGATE,
ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |

#if defined(CONFIG_MX6Q) && !defined(CONFIG_LPDDR2)

BM_ANADIG_PFD_528_PFD2_CLKGATE |

#endif

BM_ANADIG_PFD_528_PFD1_CLKGATE |
BM_ANADIG_PFD_528_PFD0_CLKGATE,
ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);

writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
BM_ANADIG_PFD_480_PFD2_CLKGATE |
BM_ANADIG_PFD_480_PFD1_CLKGATE |
BM_ANADIG_PFD_480_PFD0_CLKGATE,
ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |

#if defined(CONFIG_MX6Q) && !defined(CONFIG_LPDDR2)

BM_ANADIG_PFD_528_PFD2_CLKGATE |

#endif

BM_ANADIG_PFD_528_PFD1_CLKGATE |
BM_ANADIG_PFD_528_PFD0_CLKGATE,
ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);

...

}

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oferfederovsky
Contributor III

Hello Raymond,

Would you mind sharing the DCD configuration you have eventually used for 528MHz?

Thanks,

Ofer

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raymondwang
Senior Contributor I
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