Hi David
you can start with checking application note AN4717 (Rev. 1.0, 4/2013)
"Schematic Guidelines for the MMPF0100", sect.2 "Schematic Checklist".
http://cache.freescale.com/files/analog/doc/app_note/AN4717.pdf
Regarding start-up MMPF0100 Datasheet (rev.8, 6/2014),
for non-programmed version (MMPF0100NPAEP), Table 10 "Start-up Configuration"
defines PWRON as "Level sensitive" (PWRON_CFG = 0),
from Table 14 "PWRON Configuration" :
PWRON pin HIGH = ON
PWRON pin LOW = OFF or Sleep mode
from sect.6.4.2.1 "Turn On Events":
If PWRON_CFG = 0, the PWRON signal is high and VIN > UVDET, the PMIC will turn on
http://cache.freescale.com/files/analog/doc/data_sheet/MMPF0100.pdf
Regarding VSNVS, yes you can consider it as normal.
Its behaviour depends on many factors, described in sect.6.4.7 "VSNVS LDO/Switch".
Best regards
chip
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