Actually, the power-down sequences, shown in the Section 4.2.2 "Power-Down Sequence" of the i.MX6SoloLite Data Sheet Rev.3 document, are just the example ones. For correct chip shutdown, all supply voltages can just start to ramp down simultaneously. And, in case of momentarily removing the main power from the PF0100 PMIC, the supplies with lower output voltages and higher load, e.g. VDD_ARM_IN, VDD_SOC_IN and VDD_PU_IN core supply voltages, will ramp down faster than the supplies with the higher output voltages (e.g. I/O supply voltages). So, generally, there is no any contradiction here.
Have a great day,
Artur
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------