MMDCx_MDCFG1.tRPA[15] bit feald.

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MMDCx_MDCFG1.tRPA[15] bit feald.

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takayuki_ishii
Contributor IV

Hello,

From IMX6DQRM Reference Manual rev 3.0 to rev 4.0, tRPA bit in MMDCx_MDCFG1 register is changed

to Reserved with MMDCx_MDCFG1.Reserved[14:12].

In both document, reset value of MMDCx_MDCFG1.tRPA[15] bit seems 1.

But Field Description say that "This read-only field is reserved and always has the value 0."

Is this bit must set to 0?

Or Field Description of this reserved[15:12] is typo and value 0x8 (1000b) is correct?

Best regards,

Ishii.

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

As for tRPA parameter in MMDCx_MDCFG1 register:  
This parameter is actually a hold over from DDR2 DRAM, which defined 8-bank device Precharge All Allowance

as tRP + 1*tCK. For DDR3, Precharge all need only wait for the tRP time. So this parameter should be set to 'b0

for normal operations.


Have a great day,
Yuri

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Yuri
NXP TechSupport
NXP TechSupport

Hello,

As for tRPA parameter in MMDCx_MDCFG1 register:  
This parameter is actually a hold over from DDR2 DRAM, which defined 8-bank device Precharge All Allowance

as tRP + 1*tCK. For DDR3, Precharge all need only wait for the tRP time. So this parameter should be set to 'b0

for normal operations.


Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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takayuki_ishii
Contributor IV

Hello Yuri,

Thank you for your response.

I understand that DDR3 use same timing both tRP and tRPA.

I will report my customer it.

Best regards,

Ishii.