MIMXRT1024 GPIO interrupts

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MIMXRT1024 GPIO interrupts

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sbabu
Contributor III

Dear All,

I am using GPIO from port 3 as an interrupt. Is it possible that 2 bits can be set in interrupt status register simultaneously from 2 GPIOs? Thanks in advance.

 

Regards,

Babu

 

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sbabu
Contributor III

Dear @kerryzhou I understand I need to check in C. My doubt was "is there a possibility that 2 bits will be set at same time if there is a interrupt from 2 GPIOs" OR "Only one bit will be set at a time" ignoring or delaying the other interrupt until one of them is serviced.

Thanks,

Subash

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @sbabu ,

   GPIO3 just have 2 IRQ, so, it is determined by your used 2 pins situation.

  If you want 2 pin have the seperated IRQ, I suggest you use one is in GPIO3 pin 0-15, another is from 16 to 31.

kerryzhou_0-1688548940089.png

or, you can consider using GPIO1 pin 0 to pin 7, these 8 pins have it's own IRQ.

 

Wish it helps you!

Best Regards,

Kerry

 

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sbabu
Contributor III

Dear @kerryzhou I cannot change now as H/W is done already. We have 4 GPIOs configured as interrupt. so my question was based on this. As we have only one ISR handler for this my doubt was "do I need to check all 4 interrupt status bit one by one in the ISR or have a switch based on the bit set if only one status bit would be set. 

 

Thanks,

Babu

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @sbabu ,

  From your description, your HW used GPIO to share the same IRQ.

  To this situation, you need to check the related GPIO status, but as your used GPIO share the 32bit interrupt status register, I think you can use the C code to check it directly.

kerryzhou_0-1688550549375.png

 

Wish it helps you!

Best Regards,

Kerry

 

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sbabu
Contributor III

Dear @kerryzhou I understand I need to check in C. My doubt was "is there a possibility that 2 bits will be set at same time if there is a interrupt from 2 GPIOs" OR "Only one bit will be set at a time" ignoring or delaying the other interrupt until one of them is serviced.

Thanks,

Subash

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kerryzhou
NXP TechSupport
NXP TechSupport

Hi @sbabu ,

   It's have the possibility that the 2 pin interrupt at the same time, it is determined by your external hardware trigger situation.

  So, when the interrupt triggered, you need to check the two pin interrupt flag in the IRQ ISR, just make sure the pin interrupt is not missed.

  My understanding is, if the two pin interrupted together at the same time, as it share the same interrupt IRQ, the IRQ ISR entered one time, so I suggest you check both two pin interrupt flag.

 

With it helps you!

Best Regards,

Kerry

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