MDIO hold time issue on iMX7

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 
已解决

MDIO hold time issue on iMX7

跳至解决方案
1,534 次查看
schroeder_chung
Contributor II

Hi community,

Our customized board using iMX7 soc and run kernel 4.9.11

Recently we used vendor's new date-code PHY, we had an issue where ping sometimes fail. After we provided MDIO/MDC log, they said the hold time of MDIO is sometimes not enough. Please see the attached screen shot, the failing edge in OPcode filed should align to red line to match 802.3 spec, the hold time must be at least 10ns.

schroeder_chung_0-1705655638059.png

I read iMX7 reference manual and found there is a MII Speed Control Register can set hold time. I read the register the default value is 0x262. The hold time value is 010b. ("3 internal module clock cycles"). I try to change the hold time bits to 011. But this no any help, the failing edge no any change. Then I  change to 111, this value cause whole MDIO waveform shift and cause PHY not work.

I checked the device tree, it seems no parameter can set the hold time of MDIO. I also traced the fec_main.c, the fec_enet_mdio_read/write() call writel() to send command and writel() only save the command to FEC_MII_DATA address then return. So I don't have any idea to fix this issue.

Can someone please help me about how to change the MDIO hold time. Thank you very much.

 

标签 (1)
0 项奖励
回复
1 解答
1,442 次查看
schroeder_chung
Contributor II

Hi,

The root cause is I used lower sampling rate of logic analyzer. I used 25MS before. This is enough for MDC (2.5MHz). But hold time is 10ns, it equal to 100MHz frequency. So I should use 100MS sampling rate at least(better is 200MS, but maximum sampling rate of my analyzer is 100MS only). After I set sampling rate to 100MS, the hold time looks correct.

在原帖中查看解决方案

0 项奖励
回复
3 回复数
1,443 次查看
schroeder_chung
Contributor II

Hi,

The root cause is I used lower sampling rate of logic analyzer. I used 25MS before. This is enough for MDC (2.5MHz). But hold time is 10ns, it equal to 100MHz frequency. So I should use 100MS sampling rate at least(better is 200MS, but maximum sampling rate of my analyzer is 100MS only). After I set sampling rate to 100MS, the hold time looks correct.

0 项奖励
回复
1,500 次查看
schroeder_chung
Contributor II

Hello Salas

Yes, I modify fec_main.c where assign new value to fep->phy_speed before wirte to FEC_MII_SPEED address. I am sure this method are working, because I can change MDC to 2.083MHz when I assigned 0x276.

schroeder_chung_0-1705886951172.png

 

 

1,513 次查看
Manuel_Salas
NXP TechSupport
NXP TechSupport

Hello @schroeder_chung 

I hope you are doing well.

 

How are you modifying those values?

 

Also you can try modifying the formula for holdtime in fec_main.c

 

I hope this can helps to you.

 

Best regards.

 

Salas.

 

 

 

0 项奖励
回复