MAC57D54H - data exchange mechanism between A5 and M4

[almarto]

Hi all,

We are working on a project based on MAC57D54H and have some doubts on how to implement data exchange mechanism between cores A5 and M4: for instance speed variable is read from CAN bus and updated by M4 but it is displayed by A5. How is this variable shared by both cores? Could you please provide an example?

Thank you in advance for your collaboration.

BR,

alvaro

[jamesbone]

Hello Alvaro,

Please check the following link,  Is it possible to share the data structure between two cores A5 & M4 core in vybrid processor? 

This is using a Vybrid Processor, but it is the exactly same mechanism in the MPC5. 

Have a great day,
TIC

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