Low Frequency LVDS Pixel Clock

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Low Frequency LVDS Pixel Clock

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mike_sims
Contributor IV

Hello,

I am trying to interface a 480x272 LCD to an I.MX6DL over LVDS, but am running into problems with configuring the pixel clock in Linux.

The display I have requires a Pixel Clock of 9.5MHz, but I am unable to achieve rates below 20MHz.

Out of the box, it seems Linux wants to use PLL2_PFD0 which does not support pixel clocks below 33MHz or so.  Reading other comments on the Community site suggests using PLL5, but through experimentation, I cannot achieve rates below 18MHz.

I do see in other posts where others were seeking a similar objective, but I do not see any direct responses indicating the changes needed or patches required.

Has anyone configured a low frequency pixel clock on the i.mx6??   How can this be done???

1 Solution
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mike_sims
Contributor IV

Hi Rita,

Thank you for your quick reply.

I am using a i.mx6dl on Linux 3.14 and do not see the source code you refer to.  I did revert back all my changes and make the following changes to my device tree based on the comments in the post you referred:

&clks {
        assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
                          <&clks IMX6QDL_PLL4_BYPASS>,
                          <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
        assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
                                <&clks IMX6QDL_PLL4_BYPASS_SRC>;
        assigned-clock-rates = <0>, <0>, <24576000>;
        fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
        fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
};

&ldb {
        lvds-channel@0 {
                crtc = "ipu1-di0";
                display-timings {
                        native-mode = <&timing0>;
                        timing0: ac043na11 {
                                clock-frequency = <9500000>;
                                hactive = <480>;
                                hback-porch = <16>;
                                hfront-porch = <32>;
                                hsync-len = <12>;
                                vactive = <272>;
                                vback-porch = <12>;
                                vfront-porch = <2>;
                                vsync-len = <2>;
                                hsync-active = <1>;
                                vsync-active = <1>;
                                de-active = <1>;
                                pixelclk-active = <1>;
                        };
                };
        };

This did result in the required 9.5MHz clock....

I cannot explain why I did not see these results prior other than I had made changes to the clk-i.mx6q.c file to change the clk_set_parent.  Obvious now that I did not need this...

Thank you again for your quick reply!!!

Regards,

Mike Sims

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8 Replies
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b45499
NXP TechSupport
NXP TechSupport

Hi Mike,

You can refer to the thread Porting LVDS LCD With Low Resolution to i.MX6  in our community. Hope this can help you.

Have a nice day

Rita

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kena1
Contributor II

Rita,

I have a similar issue. I am trying to run the LVDS pixel clock at 20 MHz on a iMX6.

I am using Linux version 4.9.

The device tree and kernel source code are different and I cannot change the clock parent.

If I set the pixel clock manually using fbset on the Linux command line, the clock cannot be set lower than 26.412 MHz.

Do you have any advice?

Thank you,

Ken

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mike_sims
Contributor IV

Hi Rita,

Thank you for your quick reply.

I am using a i.mx6dl on Linux 3.14 and do not see the source code you refer to.  I did revert back all my changes and make the following changes to my device tree based on the comments in the post you referred:

&clks {
        assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
                          <&clks IMX6QDL_PLL4_BYPASS>,
                          <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
        assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
                                <&clks IMX6QDL_PLL4_BYPASS_SRC>;
        assigned-clock-rates = <0>, <0>, <24576000>;
        fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
        fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
};

&ldb {
        lvds-channel@0 {
                crtc = "ipu1-di0";
                display-timings {
                        native-mode = <&timing0>;
                        timing0: ac043na11 {
                                clock-frequency = <9500000>;
                                hactive = <480>;
                                hback-porch = <16>;
                                hfront-porch = <32>;
                                hsync-len = <12>;
                                vactive = <272>;
                                vback-porch = <12>;
                                vfront-porch = <2>;
                                vsync-len = <2>;
                                hsync-active = <1>;
                                vsync-active = <1>;
                                de-active = <1>;
                                pixelclk-active = <1>;
                        };
                };
        };

This did result in the required 9.5MHz clock....

I cannot explain why I did not see these results prior other than I had made changes to the clk-i.mx6q.c file to change the clk_set_parent.  Obvious now that I did not need this...

Thank you again for your quick reply!!!

Regards,

Mike Sims

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b45499
NXP TechSupport
NXP TechSupport

Hi Mike,

The above link is based on the Android 4.2 BSP. About the Linux 3.14 I am not sure about this. I will confirm it for you. Here you need to change the Pixel Clock. Could you please send me the datasheet of you LCD?

Best Regards

Rita

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mike_sims
Contributor IV

Hi Rita,

We are using a display that is in development, and the manufacturer has not released the specification to the general public, so I do not feel right posting it here.   The LCD is a 480 x 272 WQVGA similar to others of this geometry ours being a high brightness variant.

The above solution worked to generate a precise 9.5MHz Pixel Clock on a FSL patched Linux 3.14 (it is a long story, but we are using the FSL/NXP Android for other projects.  In this project we are using the kernel and device tree from that build).   I am in the middle of confirming the remaining signal timing, but since the Pixel Clock is correct, I suspect the remaining timing will fall into place.

I do have a remaining question though - I have heard that there a lower limits on the pixel clock when used with LDB / LVDS.  I believe a number I have read is 20MHz.   Can you confirm if there is an issue running such a slow clock on PLL5 or across the LDB / LVDS interface...

Best Regards,

Mike Sims

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b45499
NXP TechSupport
NXP TechSupport

Hi Mikel,

Low clock can work on PLL5 when use the LVDS/LDB interface, in the Porting LVDS LCD With Low Resolution to i.MX6  you can see that my colleague has made the 6.4MHz low resolution LVDS work to i.mx6 on andorid 4.2.2 version BSP. About the new linux BSP you'd better have check you setting .

I see that you have already setting up the pll5:

fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
 fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;

You need to confirm if it is working.

Have a nice day

Rita

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mike_sims
Contributor IV

Hi Rita,

Sorry for the long time for my reply...   Yes, I can confirm that this was the only change required and I am getting the correct clock and remaining display timing.

I am having some additional problems, but because they are not clock related, I have posted them under a new question.   The issue is that in the above work, I was configured for RGB666.   The display I have is 24bit, so I thought I could change the RGB666 to RGB24 to get the additional color data for the display...   This is not working and has resulted in a very messy display.   If this is something you can help with, the new post is located here --> https://community.nxp.com/message/836916

Thank you again for all your wonderful help!!

Regards,

Mike Sims

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b45499
NXP TechSupport
NXP TechSupport

Hi Mike,

OK,  I will confirm it for you, and then give you reply.

Have a nice day

Rita

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