Looking for app notes for ECSPIx SPI NOR boot effort?...

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Looking for app notes for ECSPIx SPI NOR boot effort?...

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djregan
Contributor III

Hello,

We are looking for application notes to assist with custom board bring-up efforts. Specifically, for IMX6ULL with configuration to support SPI NOR ('Serial ROM') boot on a ECSPIx port.

The problem we are attempting to diagnose... We are not seeing a successful 1st stage program loading outcome.

We are seeing signs-of-life (good things) from observing 1st stage program loading efforts:

- After reset, we see the expected ECSPI SCLK activity during 'Serial ROM' boot up (15MHz / correct for 3-byte SPI addressing Modes).

- About 8 milliseconds after reset recover, we observe the 1st ECSPI SCLK pulses begin to be visible.

ecspi_after_8mSec.jpg

- ECSPI clock activity indicates data is being streamed from SPI NOR for 3.4 milliseconds (at the 15MHz clock rate)

ecspi_3.4mSec_read_effort.jpg

We know the DDR RAM connection to the IMX6ULL is good, and we can use Segger JLink JTAG adapters to pre-initialize DDR with uBoot, and run uBoot without the IMX6ULL's 1st stage program loader (without 'Serial ROM' boot)... so, we know need to diagnose reasons 'why?' the 1st stage program loader may not be successful.

We also know the data image within the ECSPIx connected SPI NOR flash is per our intended memory image, We are able to use uBoot 'sf probe', 'sf erase', 'sf write', 'sf read' commands to erase, burn and read back the SPI NOR targeted image.

Does NXP offer any App Notes which can help customers diagnose 1st Stage Program Loading Efforts, and... specifically for folks leveraging an ECSPIx port with a SPI NOR memory interface?

Thanks much in advance,

--DJ Regan

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igorpadykov
NXP Employee
NXP Employee

Hi DJ Regan

I am afraid such document is not available, in general common steps

would be to check SRC_SBMR1,2 with jtag for correct boot selection.

Dump 0x907400 (ROM uses 0x907000 as starting address),
one should see IVT header here if the device boot access is ok, as described on:

i.MX6Q NAND boot issues 

Other test steps: prolong POR up to 1sec., reconfigure image to fit to OCRAM

and run it from OCRAM, for example toggle some gpio.

Best regards
igor
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djregan
Contributor III

Hi Igor,

Thanks so much for your advice sir! We figured out what we did wrong... although I've read, re-read, the need to write the initial load region data beginning at hex offset 0x400, I didnt do it yesterday.

So... after re-erasing the SPI NOR Flash, leaving the 1st 0x0 through 0x3FF bytes blank (0xFF), and writing our initial load region plus uBoot executable starting from 0x400 ---> SUCCESS! :smileyhappy:

Appreciate it Igor!

Thanks again,

--DJ

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