Leak voltage to USB_OTG_DP / N during the reset.

[takashitakahash]

Hi community.

Our customer has question below.

To ask  about the leak voltage to USB_OTG_DP / N during the reset.

Please see atached Fig.

Currently, leak voltage will have occurred  from the outside, on the system (actual device) USB_OTG_DP / N.

Leak voltage is about 0.3V, but we are concerned about the latch-up and reverse current flow occurs because it has been applied to the PowerSpurce (USB_OTG_VBUS and VDDUSB_CAP) before the launch of the USB_OTG_DP / N.

Would you please advice to me, Is it necessary for the latch-up and the current back-flow measures or accepable range .

Thasnks,

Best.

T.Takahashi

[igorpadykov · Accepted solution]

Hi Takashi

this is smal voltage should not cause problems, also

it is less then Vil from Table 7-7 USB 2.0 specification.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------