LVDS pixel clock on i.MX6

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LVDS pixel clock on i.MX6

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elenagarcia
Contributor I

Hi, all,

I need a frequency of 33 MHz for the LVDS clock signal.

I have added the following mode to the ldb_modedb[] array in /drivers/video/mxc/ldb.c:

{

     "LDB-LG", 60, 800, 480, 30066,

     64,64,

     30, 5,

    128, 10,

    0,

     FB_VMODE_NONINTERLACED,

     FB_MODE_IS_DETAILED,},

};


In sys/class/graphics/fb0/mode I can see that the resolution is correctly set, but the frequency I can see with the oscilloscope for the LVDS clock is 38 MHz instead of the 33 MHz I want to set in the array. Because of this the display doesnt work.


Does anyone know about this issue?

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fabio_estevam
NXP Employee
NXP Employee

Your analysis is correct. You need to use another parent for the ldb clock instead of pll2.

Please look at: https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/arch/arm/mach-imx/clk-imx6q.c?...

The following clocks can be the parent of ldb_di_sel clock:

static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };

Then you can use clk_set_parent to select a different parent. On the case of kernel mainline, pll5 is set as parent:

clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);

Regards,

Fabio Estevam

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fabio_estevam
NXP Employee
NXP Employee

If you want 33MHz the fifth parameter of the first line should be 30303, which is 1 / 33 MHz in pico seconds.

Hope this helps.

Regards,

Fabio Estevam

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michaelschanz
Contributor III

Hi Fabio,

thank you for your reply. Unfortunately, your information doesn't help much.

You're absolutely correct - 33MHz equates to 30303 pico seconds. However, the question is rather: how to configure the i.MX6 clock distribution that LVDS clock frequencies lower than 38.79 MHz can be achieved?

Please correct me if I'm wrong, but as far as I understand, the LVDS clock frequency is derived from the System-PLL (PLL2), PFD0. PLL2 runs with 528MHz and for the selector of PFD0 a value between 12 and 35 can be chosen. So the lowest selectable frequency for PFD0 seems to be 271.5 MHz (528MHz*18/35). Finally, the LVDS clock is derived from a subsequent fixed divider by 7, so 271.5MHz / 7 = 38.79MHz - this is exactly the value that we measure. In the linux kernel, the function clk_round_rate() (see ldb.c, fct ldb_disp_setup()) seems to be responsible to determine the nearest LVDS clock rate according to the specified value. This function returns the lowest possible value (which is 38791836), regardless if 30303 or if 30066 is configured.

I'm afraid, but if above assumption is correct, the LVDS clock can't be less than 38.79MHz with the current clock setup, right? If I'm correct, all LVDS panels that require less than 38MHz LVDS clock frequency (most of the 800x480 and most likely all of the 640x480 panels) might not work on the LVDS port. So, how is it possible to configure the system (respectively the clock distribution) in order to achieve LVDS clock frequencies of 33MHz (and even lower, e.g. 25MHz)?


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karina_valencia
NXP Apps Support
NXP Apps Support

FabioEstevam can you continue  the follow up on this case?

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fabio_estevam
NXP Employee
NXP Employee

Your analysis is correct. You need to use another parent for the ldb clock instead of pll2.

Please look at: https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/tree/arch/arm/mach-imx/clk-imx6q.c?...

The following clocks can be the parent of ldb_di_sel clock:

static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };

Then you can use clk_set_parent to select a different parent. On the case of kernel mainline, pll5 is set as parent:

clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);

Regards,

Fabio Estevam

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scott10
Contributor II

Hi Fabio and Freescale Community,

Thank you for the information, it was very helpful in changing my LVDS pixel clock!

I still have a few remaining questions hopefully someone can answer:

  1. It seems as though the only way to change the LVDS pixel clock is by changing the clock parent and any inline dividers along the way. This means that we have a fairly limited possible set of pixel clock frequencies. Is my understanding correct?
    • If so, does software just ignore the pixel clock period in picoseconds that we provide?
  2. I see that register "DI0 General Register (IPUx_DI0_GENERAL) 0x0264_0000 gives the ability to select the source for the VSYNC and DI0 clock signal. The two options are External to the IPU or Internally generated by the IPU.
    • If I clear these bits to select the source as internally generated by the IPU, are there then registers to configure the pixel clock frequency?
    • Perhaps I am just missing them and this would allows fine tuning of the pixel clock...

I realize this is an old thread, but hopefully it still gets attention.

Thank you,

Scott

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samarthmehta
Contributor II

Hi Fabio,

I have a very similar problem.  I am getting 66 MHz on LVDS clock and I am looking for 33.26 MHz.  My LCD is working, but 66 MHz is out of spec for LCD and it puts noise on our boards. 

I am using i.MX53 and freescale version of Linux kernel 2.6.35.

Can you please guide me where I need to change clock frequencies to achieve 33.26 MHz?

Thanks

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stephanhoffmann
Contributor II

Hello all,

did anybody manage to get a lower pixel rate?

According to Fanio's advice I changed the parent clock to mmdc_ch1_axi, because this seems to be the only one that can be tuned to a lower frequency, but now my system stops responding as soon as this clock is changed, even though I cannot find any other place where it is used:


Part of mx6_clocks_init():

...

        clk_set_rate(&pll2_pfd_352M, 413000000);
        clk_set_parent(&mmdc_ch1_axi_clk, &pll2_pfd_352M);
        clk_set_parent(&ldb_di0_clk, &mmdc_ch1_axi_clk);
        clk_set_parent(&ldb_di1_clk, &mmdc_ch1_axi_clk);
//      clk_set_rate(&mmdc_ch1_axi_clk, clk_round_rate(&mmdc_ch1_axi_clk, 206500000));
// if I uncomment above line the system does not respond any more

...


BTW: I am stuck to 3.0.35 because board support for a newer kernel is not yet availeable.


Does anybody have any idea what else I can do?


Kind regards


Stephan


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fabio_estevam
NXP Employee
NXP Employee

Stephan,

Please use pll5 as the source of the LDB clock. What is the pixeclock that is required by your LVDS panel and what is the value that you achieve?

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stephanhoffmann
Contributor II

Thank you, Fabio, for your quick help!

I actually misunderstood your earlier answer and so got on the wrong way. Using pll5 really gives the correct frequency.

The setting I started with (pll2_pfd_352M as parent) had been introduced with patch ENGR00174649 for i.mx6dl and extended in ENGR00179647 for all architectures and had been there since then;-)

Kind regards

Stephan

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schnirom
Contributor I

Hello,

I have the save problem with a display that needs a pixel clock of 9MHz (4.3", 480x272). I already set the parent for ldb_di0_clk to the Video PLL.

With this setup I get the lowest frequency of 23.3MHz. Any hints what I need to do to get a 9MHz clock?

My additional fb_videomode in ldb_modedb is:

     {"DLC-4.3", 60, 480, 272, 111111,
     2, 2,
     2, 2,
     41, 10,
     FB_SYNC_CLK_LAT_FALL,
     FB_VMODE_NONINTERLACED,
     0,},

Thanks,

Roman.

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andy_woetzel
Contributor I

Hello,

I have the exact same problem on a windows embedded system (I need 9 MHz pixel clock over LVDS). With PLL5 as clock parent, I am able to achieve a minimal LVDS serializer clock of 168 MHz, which results in a pixel clock of 24 MHz.

I think it could be possible to achieve a lower clock by using mmdc_ch1_axi as clock parent, but am unable to do this in windows embedded at the moment (mmdc_ch1_axi is not fully supported in the BSP yet).

Has anybody tried this successfully in linux?

Also, I am concerned about the clock sources and range of the LDB as stated in the reference manual: "DI0_CLK, DI1_CLK- Display interface clock: 20-150 MHz" and "DI0_SER_CLK, DI1_SER_CLK - Serializer clock: 140-595 MHz". Does this really mean that displays with a required pixel clock of less than 20 MHz are not supported using LVDS?

Thanks,

Andy

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