LSIO GPIO Driver in SCFW 1.1 not working

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LSIO GPIO Driver in SCFW 1.1 not working

799 Views
vmuthusu
Contributor III

We have our custom board based on iMX8QXP. We are using the SCFW1.1. Trying to toggle a LSIO GPIO pin using the GPIO Driver interfaces provided in the SCFW documentation.

But the GPIO driver is accessing a different register base address that corresponds to FGPIO instead of the GPIO.

For e.g 

scfw_export_mx8qx_b0\platform\drivers\gpio\fsl_gpio.h

static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)
{
if (output == 0U)
{
base->PCOR = 1 << pin;
}
else
{
base->PSOR = 1 << pin;
}
}

The PCOR and PSOR are not part of LSIO GPIO subsystem as per the reference manual.

Is the LSIO GPIO is not supported in the current SCFW1.1 version?

If so is there a plan to support in the future versions?

5 Replies

181 Views
vmuthusu
Contributor III

Hi 

When i click on the "Branched to a new discussion" link above i am getting unauthorized error.

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181 Views
CarlosCasillas
NXP Employee
NXP Employee

Hi,

I internally received the following information:

The scfw_export_mx8qx_b0\platform\drivers\gpio\fsl_gpio.* driver is specific only for SCU GPIOs and for LSIO GPIO.

Generally, the above steps should be done if you want to program LSIO GPIO from SCU.

 

0. Since LSIO GPIO belongs to other subsystem then SCU, please power DB cross switch in order to be able to access LSIO IPs from SC.

0.1 Mark LSIO GPIO resource as nonmovable if you need to keep it in SCU partition.

1. Set the mux ( example: pad_set_mux(SC_PT, SC_P_ADC_IN5, 4, SC_PAD_CONFIG_NORMAL,  SC_PAD_ISO_OFF) );

2. Power up the resource ( example:  pm_force_resource_power_mode(SC_R_GPIO_1, SC_PM_PW_MODE_ON); )

3. Program specific PIN (direction, value etc):

a.  With Structure

/* LSIO GPIO registers */
typedef struct {
__IO uint32_t DR; /* Data Register */
__IO uint32_t GDIR; /* Direction Register */
__IO uint32_t PSR; /* Pad Status Register */
__IO uint32_t ICR1; /* Interrupt Configuration Register 1 */
__IO uint32_t ICR2; /* Interrupt Configuration Register 2 */
__IO uint32_t IMR; /* Interrupt Mask Register */
__IO uint32_t EDGE_SEL; /* Edge Select Register */
} LSIO_GPIO_Type;

#define LSIO_GPIO0 ((LSIO_GPIO_Type *) 0x5D080000)
#define LSIO_GPIO1 ((LSIO_GPIO_Type *) 0x5D090000)
#define LSIO_GPIO2 ((LSIO_GPIO_Type *) 0x5D0A0000)
#define LSIO_GPIO3 ((LSIO_GPIO_Type *) 0x5D0B0000)
#define LSIO_GPIO4 ((LSIO_GPIO_Type *) 0x5D0C0000)
#define LSIO_GPIO5 ((LSIO_GPIO_Type *) 0x5D0D0000)
#define LSIO_GPIO6 ((LSIO_GPIO_Type *) 0x5D0E0000)
#define LSIO_GPIO7 ((LSIO_GPIO_Type *) 0x5D0F0000)

 

Direction

 uint32_t lsioGpioMask = BIT(13);

  LSIO_GPIO1->GDIR |= lsioGpioMask;

Toggling:

 

/* Toggle GPIO outputs each 1 sec */
for (uint i = 0; i < GPIO_TOGGLE_SEC; i++)
{
      if (LSIO_GPIO1->DR & lsioGpioMask)
         LSIO_GPIO1->DR &= (~(lsioGpioMask));
      else
         LSIO_GPIO1->DR |= lsioGpioMask;

      SystemTimeDelay(1000000);
}

b. Direct accessing the memory:

Direction:

(*((int *)0x5D090004)) |= (1<<13);

Toggling:

 

for (int i = 0; i <GPIO_TOGGLE_SEC; i++) {
   if( (*((int *)0x5D090000)) & (1<<13))
       (*((int *)0x5D090000)) &= ~(1<<13);
   else

   (*((int *)0x5D090000)) |= (1<<13);

      SystemTimeDelay(1000000);

}

 

The Architecture of SCFW porting provides the flexibility to add your own drivers if there are needed in boards/mx8qx_* directory.

Hope this will be useful for you.
Best regards!
/Carlos
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181 Views
liuxi
Contributor I

Hi Carlos

 I try your suggestion,operation GPIO4_25 in SCFW with the I.MX8 QM。

When I operation LSIO_GPIO4->GDIR,SCFW stoped。

Can you give some advices?

Thank you very much!!

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181 Views
vmuthusu
Contributor III

Hi Carlos

Thanks for your reply and help.

I will try out the suggestion and get back if in case any issues.

Thanks

V.Muthusubramanian

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181 Views
CarlosCasillas
NXP Employee
NXP Employee

Hi,

I internally asked to confirm the features of the SCFW, because the M4 dedicated to the SCU includes a dedicated UART, I2C and HSGPIO (the one that seems you are seeing) that are not accessible to the user A and M cores, but just want to confirm if the regular GPIOs of the SoC are accessible from the SCU.

I will post an update as soon as having news.

Best regards!

/Carlos

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