LPUART2 not usable on i.MX95 - kernel crash when enabling

[Samt07]

Hi all,

I'm working on a i.MX95 board, and I'm running into issues enabling LPUART2 from Linux.

I've added the following to my board-specific .dts:

&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};

(this much should work as other uart working with similar changes)

The pinctrl is properly defined and the DT compiles correctly. However, during kernel boot, I get this error:

scmi-pinctrl scmi_dev.6: Error parsing config -13
scmi-pinctrl scmi_dev.6: pin_config_set op failed for pin 119
fsl-lpuart 44390000.serial: Error applying setting, reverse things back
Internal error: synchronous external abort: 0000000096000010 [#1] PREEMPT SMP

If I disable LPUART2, the kernel boots normally.

So I'm wondering if something in the system or firmware is preventing access to this UART from the Linux side.

Appreciate any insights, thanks!

[Chavira]

HI @Samt07!

Thank you for contacting NXP Support!

Can you share your device tree file?

What board are you using?

What BSP version are you using?

[Samt07]

using iWave iW-RainboW-G61D 
Version: Linux6.6.36

SOM level: my imx95-iwg61m.dtsi

&lpuart2 {

    pinctrl-names = "default";

    pinctrl-0 = <&pinctrl_uart2>;

    status = "okay";

};

pinctrl_uart2: uart2grp {

    fsl,pins = <

IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX      0x31e

IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX      0x31e

IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x31e

IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x31e

    >;

};

Let me know if you'd like me to share the full DTS file or any kernel logs again.

[Chavira]

HI @Samt07!

Yes, I need the full device tree file (dts and dtsi files)

[Samt07]

Hi,
please find the attached files.  i see some comments about M33 uart which i suppose means LPUART2 is assigned to the M33 core, and i am not sure how can i use uart2.

[Chavira]

Hi @Samt07!

What boards are you using?

Your board are using the UART2 for M core?

[Samt07]

>> Your board are using the UART2 for M core?

I'm not entirely certain how the core ownership is configured on this platform, but based on the imx95-iwg61m.dtsi file, UART2 is commented as // M33 UART , which suggests that it may be allocated to the M core (Cortex-M33).

If that’s the case, I assume the UART2 peripheral might be under the control of the M core, and that could explain the issue when the A core tries to configure or access it.

Could you please confirm if UART2 is reserved for the M core by default in this SoC? If so, I’d like to understand the proper method to reassign or release it for use by the A core. Is it done via SCMI resource partitioning or any specific firmware configuration?

For reference, during kernel boot, I'm getting the following error:

i have already shared the error snippet while kernel is starting that 
scmi-pinctrl scmi_dev.6: Error parsing config -13
scmi-pinctrl scmi_dev.6: pin_config_set op failed for pin 119
fsl-lpuart 44390000.serial: Error applying setting, reverse things back
Internal error: synchronous external abort: 0000000096000010 [#1] PREEMPT SMP

This seems to point toward either access permission issues or improper ownership configuration.

>>What boards are you using?
I am using iwave i.MX 95 SMARC SOM

[Chavira]

Hi @Samt07!

The iMX95 could contain embedded the binary of M core in the boot loader image..

I recommend to ask to iWAVE how to remove the image of the M core of their image to use the UART2 in A core.

Both processors can´t use the same peripheral because can cause kernel panics.

Is a normal behavior and that happens in iMX8M too when the peripherals are taken by two different cores.

Best Regards!

Chavira