Hello,
I am using below part numbers.
1. LPDDR4 of Micron part no. MT53D512M32D2DS-046 IT:D with config 512M32 i.e. size 16Gb
2. IMX8M-Quad
Custom H/w interface: 32 DQ lines of IMX8M-Quad to interface with 2 channels of LPDDR4 using two CS0_A, CS0_B as we are using 512M32 [Note: CS1_A, CS1_B: Added in H/w for future]
We are using below NXP tools and guidelines
1. MX8M_LPDDR4_RPA_v30.xlsx - https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX8M-m850D-DDR-Register-Programming-Ai...
2. MSCALE_DDR_Tool_User_Guide.pdf (IMX Rev. V2.0.0 1/23/2021) - https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/110...
[QUERY-1]:
We feel bit unclear about parameter 'Number of Channels' and 'Total DRAM Density'. In our scenario, we set below parameters using datasheet of MT53D512M32D2DS-046 IT:D (size 16Gb)
a. Bus width : 32
b. Number of Channels (Auto-compute) : 2
c. Density per channel per chip select (Gb): 8 Gb
d. Number of Chip Selects used : 2
e. Total DRAM density (Gb)(Auto-compute) : 32
f. Clock Cycle Freq (MHz) : 2133 (because of speed-grade 046)
g. Clock Cycle Time (ns) (Auto-compute) : 0.468823254
In DDR tool user guide, parameter 'Number of Channels per chip select' is present.
Request you please guide on above unclear parameters 'Number of Channels' and 'Total DRAM Density' and validate the correctness.
[QUERY-2]:
In MSCALE_DDR_Tool.exe,
a. Target drop-down has 4 options. In our case, we have MIMX8-Quad so we selected 'MX8M'
b. Clock drop-down has 4 options (including Default). Please guide which one to select
c. Density has list in drop-down. Please guide which one to select referring to part.e of QUERY-1
