Hi,
I am using 4GB LPDDR4 (MT53E1G32D2FW-046 IT:C) on iMX8MP custom board.
While performing DDR calibration with MSCALE tool, I am facing below issue.
Download is complete
Waiting for the target board boot...
===================hardware_init=====================
********Found PMIC PCA9450**********
hardware_init exit
*************************************************************************
*************************************************************************
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MX8 DDR Stress Test V3.30
Built on Nov 24 2021 13:52:12
*************************************************************************
Waiting for board configuration from PC-end...
--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug
- VMCR Check:
- ttbr0_el3: 0x97d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122
- MMU and cache setup complete
*************************************************************************
ARM clock(CA53) rate: 1800MHz
DDR Clock: 2000MHz
============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 17, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 4096MB
Density per controller is: 4096MB
Total density detected on the board is: 4096MB
============================================
MX8M-plus: Cortex-A53 is found
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============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @2000Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @200Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @50Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @2000Mhz...
[Process] End of initialization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Result] PASS
============ Step 2: DDR memory accessing... ============
Verifying DDR frequency point0@2000MHz......Address of failure: 0x0000000040080000
Data read was: 0x0000000040000010
But pattern was: 0x0000000040000000
Failed
Please modify DDRC/DFI parameters!!!
NXP iMX/MSCALE tool Version - 3.31
iMX8MP RPA Tool version - v9
The DDR configuration updated on RPA tool as below for reference.
Please someone can help how to fix 'Please modify DDRC/DFI parameters' for LPDDR4 on IMX8MPLUS board.
Regards,
Prashanth K
