We got a board with LPDDR3L, we used the spreadsheet for
i.MX6 sololite for generating a DCD table. I can load the uboot using
usb_loader and able to trace it. The uboot went through all the
initializations in board.c (board_init_f) except calling the last
function (dram_init). I also confirmed that the DCD table was called
during the uboot initialization because I added a function to change
the state of my GPIO pin.
//gpio_toggle1(); -- enabling the said function it works
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
//gpio_toggle1(); - enabling the said function and disabling the function above, I didn't see the toggle on my scope
Then, I added a gpio_toggle (infinite loop) function in dram_init.
Enabling the first function call, the toggling of the pin works. Then,
I disabled the first one and enabled the 2nd function, it did not run.
Maybe the get_ram_size function crashes because the DDR3 was not
Right now, I have no idea how to verify if the DDR3L has been
initialized correctly or not. I would like to know if you can give me
some pointers or any program to verify the initialization?.
Solved! Go to Solution.
You mentioned a spreadsheet tool to generate your DCD. I can't find it on the Solo-Lite product site, the forum or even with Google searches. Could you please be so kind to point me to a location where to find it?
Please contact you FAE to send you a copy.
Here You have mentioned that you have used the spreadsheet for i.MX6 sololite for generating a DCD table. Can you please explain how you have generated this DCD table.
We are also using DDR3 (K4B2G1646E-BCK0) with imx6 sololite for our board and facing a reset issue in DDR. So i need the spreadsheet to crosscheck my DDR3 configuration.
Fill up the "Register Configuration" sheet, once your done on that sheet, click the "RealView.inc file". Copy the contents of the said sheet and convert it into uboot DCD format.
wait = on
// Disable WDOG
setmem /16 0x020bc000 0x30
setmem /32 0x020e030c = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
setmem /32 0x020e0310 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
setmem /32 0x020e0314 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
setmem /32 0x020e0318 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
u-boot DCD.conf format:
//wait = on
// Disable WDOG
//setmem /16 0x020bc000 0x30
DATA 4 0x020e030c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
DATA 4 0x020e0310 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
DATA 4 0x020e0314 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
DATA 4 0x020e0318 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
Then, you have to replace the content of board/freescale/mx6slevk/imximage.cfg in uboot (Assuming your board is based on mx6slevk). But, I would suggest you have to create a new board definition for your board in uboot.
I hope it helps.
When you load uboot, you can add a forever loop at the beginning of dram_init, then use JTAG connect to the board, access the dram to see whether you can read or write dram, the dram address should be starting from 0x80000000. If you don't have JTAG available, just replace the GPIO toggle with dram read/write. If dram is ok, then this issue shou be a pure SW issue, easy to fix.
Just to confirm whether dram has been initialized successfully, then we can discuss how to proceed next step.
It works, I can write data in memory location 0x80000000. May I know what's the next step then?
for gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);, I think the get_ram_size function only return a value, right? So it does NOT make sense that uboot will hang here, unless that gd struct is in the wrong address, besially, this gd sturct should be defined at the head of uboot, I meant, currently for i.MX6 sololite, the uboot load address should be 0x80800000, so gd should be at he location of 0x80000000 ~ 0x80800000, so can you comment out this line, and only print out the gd address? printf("gd addr 0x%x\n", gd); Let's make sure it is in the right address.
So you may first print out the gd addr and the return of get_ram_size to see whether they both OK.
I am missing some part at this time to enable the UART, JTAG and scope is my tools at this time.
Btw, I am using the said uboot on my other custom board, although other board is using LPDDR2 and other is LPDDR3L. I am using the same board configuration except on the other one, I used the DCD for LPDDR3L.
I was trying to imagine why the code is breaking at that routine after changing the DDR?.
Our project is about to start. We are going to integrate DDR3 with Sololite too.
So, to port DDR3, all you had to do was replace DCD table in flash_header.S? No other change in boot loader ?
Could you please tell what kernel modifications need to be done for DDR3 integration?
It looks to me the gd is causing the problem. Any idea how to fix it?.
Can you tell the what is the gd address? Start with 0x10......? Maybe you need to check the config of TEXT_BASE? I want to know the TAXT_BASE of your config, maybe it is not in the valid address of dram.
Sent from my iPad
在 2013-7-14，13:03，"John Tobias" <email@example.com<mailto:firstname.lastname@example.org>> 写道：
LPDDR3L for i.MX6 sololie
created by John Tobias<https://community.freescale.com/people/jtobias> in i.MX Community - View the full discussion<https://community.freescale.com/message/339858#339858>
The gd is 0x93fea8 and TEXT_BASE is 0x87800000
That is weird, gd should be configured as : gd = (gd_t*)(_armboot_start - CONFIG_SYS_MALLOC_LEN - sizeof(gd_t));
And _armboot_start should be 0x878......, so your gd address is incorrect.
I don't know how you build the uboot and got wrong gd address. From this value, it is in OCRAM space, please check your config. I think there must be something wrong during your porting.
I got it working now.. thanks for the help.
Great news. May I know the root cause?
BTW, please set this ticket/question as closed, thanks.
It turns out that uboot didn't like sharing a board (board/myIMX6SL-board) resources in two different configurations.
Since I have two boards with identical configuration except for DDR, I used it to build my image for my board with LPDDR2 and LPDDR3L.
In my make file, I call:
make .... my_configuration_ddr3_config - for building the image with correct DDR3 DCD configuration file.
make my_configuration_lpddr2_config - for build building the image with correct LPDDR2 DCD configuration file.
After separating the LPDDR3, it works as is.
In my boards.cfg, I have two settings