LPDDR3 Access Failed CPU up to 1GHz

[kejieyu]

Hello,
Changed i.MX6Q PLL1 by set register 0x020c8000 by value 0x80002053 to 1GHz for ARM core. But, there is sporadically memory access failed, Tested by memtester version 4.3.0 (32-bit).

But, when set CPU clock back to 800MHz, everything became ok. and I check the data sheet of the i.MX6, the processor we selected support the high CPU frequency up to 1GHz. and the PLL1 and PLL2 seemly independence between with each other as the data sheet described.

Is there any other setting needed for the change of the CPU to 1GHz? Is there anything impact the DDR access? I have already made calibration by ddr_stress_tester_v2.60 (NXP).

Is there any missing about the setting of Power and Clock?

Best Regards

Yu.

[igorpadykov]

Hi Yu

i.MX6Q does not support lpddr3 memory. As for errors at higher arm core

frequencies - they may be caused by increased board power supplies noise -

please check i.MX6 System Development User’s Guide, Chapter 4
Requirements for Power Management, check with oscillosope ripples and

compare with its requirements provided in Table 2-6. Power and decouple recommendations

https://www.nxp.com/docs/en/user-guide/IMX6DQ6SDLHDG.pdf

Best regards
igor
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