Strictly speaking, JEDEC provides pad sequence standardization for LPDDR2 :
Ordering of DQ bits shall be maintained in the system, including within the
package and on the PCB. DQ byte swapping and DQ bit Swapping are not allowed in
the system.
And MCIMX6SLEVK design follows such approach. In the same time i.MX53 design
with LPDDR2 does not : byte and bit within byte swapping is applied there.
Have a great day,
Yuri
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