LPDDR2 iMX6S/DL configuration and calibration problem

[Astralix]

I have to start u-boot on a new board, unfortunately the design was not based upon usual dev-boards...

It uses two MT42L128M32D1 LPDDR2 SRAMs on iMX6DL, one for low word DRAM_D0..31 on port 0 and the other one for the high word DRAM_D32..63 at port 1.

I cannot find the right configuration option for that or an appropriate DDR config Excel sheet.

And finally the promising LPDDR stress test tools, provided here, are using UART1 but my design uses uses UART5 on CSI0_DAT14 (TX) CSI0_DAT15 (RX).

There is a second design using the same basics, but is equipped with iMX6S and only port 0 has a MT42L128M32D1 placed but it uses UART5 too.

[Astralix]

Hello Yuri,

just to close this case in the official forum: The major problem was a power supply issue with the LPDDR3 DRAM. The NVCC_DDRAM supplies where not powered correctly.

After solving that issue, the modified lpddr3_stress_test tool did its job and we have LPDDR3-DRAM working fine.

Thank you for your support.

Ulrich

[Yuri]

  Please look at my comments below.

1.
  I am afraid, Your configuration is not working, since the i.MX6 DL supports dual

channel 2x32-bit for LPDDR2, but both channels use DRAM_D0..31.

2.

  It is possible to build the Stress Tester with uart-option as UART1_1 or UART2_1.

If this option is not specified, UART4 is used as default. Sorry, UART5 is not supported.

Have a great day,
Yuri

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[Astralix]

Hello Yuri,

thank you for your support.

as you might have seen, I will have long discussions with hardware team the next days. However, I'd like to verify the rest of the hardware so I go for initializing the low-word LPDDR2 chip, only just to get u-boot working enough to toggle some GPIOs and such.

You wrote, that the DRAM Stress-Test works on UART4 and optionally UART1 or 2. I only found these versions here i.MX6 DDR Stress Test Tool V1.0.3 and I guess the normal non-SD version should talk to UART4?

Our board does not have USB OTG, so I test-wise put the tool to an SD card like I do with u-boot normally. I expected at least some communication on UART4 even without having the PC Tool running, but I cannot detect a single bit.

In the description I only found USB OTG as communication partner for the windows tool... As I told above, we do not have that option.

kind regards

Ulrich

[Yuri]

Hello, Ulrich !

Please look at my comments below.

1.

> [...] the normal non-SD version should talk to UART4?

The normal non-SD version, located in the Community, works via USB OTG.

2.
  As mentioned : "If  USB OTG port is not available on customer board, please use
the images in DDR_Stress_Tester_V1.0.3_UART1_for_SDboot&JTAG.zip".

Regards,

Yuri.

[Astralix]

Thanks again, Yuri.

But I have to get back to the LPDDR2 DRAM connection design:

According IMX6SDLIEC page 5 you can read:

• External memory interfaces: The i.MX 6Solo/6DualLite processors support latest, high volume, cost effective handheld DRAM, NOR, and NAND Flash memory standards. — 16/32-bit LP-DDR2-800, 16/32-bit DDR3-800 and LV-DDR3-800 in i.MX 6Solo; 16/32/64-bit LP-DDR2-800, 16/32/64-bit DDR3-800 and LV-DDR3-800, supporting DDR interleaving mode for 2x32 LPDDR2-800 in i.MX 6DualLite

In the IMX6SDLRM on page 201 you can read:

• In i.MX 6Solo, 16/32-bit LP-DDR2-800, 16/32-bit DDR3-800, and LV-DDR3-800

• In i.MX 6DualLite, 16/32/64-bit LP-DDR2-800, 16/32/64-bit DDR3-800, and LV-DDR3-800

In the IMX6SDLRM on page 207:

Memory, 800 MT/s per Line, supports LP-DDR2 (2x16, 2x32, 2x32 interleaved mode - x64), DDR3 (x16/x32/x64) and DDR3L (x16/x32/x64)

For me that sounds as you can attach 64 bit wide LPDDR2 DRAM memory to the iMX6DL. Alternatively you can add 2x32bit wide memory for interleaving. We are aware that it is not possible to do this at the iMX6S as it only supports one PHY, but the iMX6DL has two PHYs.

We layouted a single PCB that supports both SOCs (iMX6S and iMX6DL) and offers two landing patters for MT42L128M32D1 LPDDR2 DRAM chips. Can you verify our design or can you send me a reference design that shows how to implement this? The iMX6S should only use the 32bit and one DRAM chip while the iMX6DL should have 64bit access to both chips in parallel.

Kind reagrds

Ulrich

[Yuri]

Please send me the schematic for review (under SR # 1-3640236178)

Regards,

Yuri.