LPDDDR4 Training fails at low frequency (400 MHz/ 1000 MHz)

[NikJur]

Hi,

We have copied the schematic and layout of a previous board with exactly the same SOC and LPDDR4 chip: IMX8MP + MT53E1G32D2FW-046 AIT:C. It worked flawlessly until 1800 MHz.

For the new board, despite the fact that for the RAM-initilization the working frequency was reduced to 1000 MHz and 400 MHz  the firmware init test in the ConfigTool25.09 fails. The same holds for the mscale ddr tool: 

I got two errors for two different firmware training settings:

1) Default  setting in the RPA sheet

ddrparam set

TrainCtrl0

0x131f

1d-Training fails and i got the following debugging message. From that i would deduct that CS0 is causing troubles. However the bitmap dump and the meaning of it is not described in the imx config guidelines. Could you describe the following bitmap dump and what could be a measure to eradicate the failed 1d-CA-Training? Are full lines of ff good or bad? Are 0´s good or bad? 

[1] PMU5: CA bitmap dump for cs 0
[1] PMU5: CAA0 [1] ff[1] ff[1] ff[1] fe[1] 00[1] 00[1] 00[1] 00[1] 00[1] 00[1] 00[1] 03[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1]
[1] PMU5: CAA1 [1] ff[1] ff[1] ff[1] fe[1] 00[1] 00[1] 00[1] 00[1] 00[1] 00[1] 00[1] 03[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1]
[1] PMU5: CAA2 [1] ff[1] ff[1] ff[1] fe[1] 00[1] 00[1] 00[1] 00[1] 00[1] 00[1] 00[1] 03[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1]
[1] PMU5: CAA3 [1] ff[1] ff[1] ff[1] fc[1] 00[1] 00[1] 00[1] 00[1] 00[1] 00[1] 00[1] 07[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1]
[1] PMU5: CAA4 [1] ff[1] ff[1] ff[1] fe[1] 00[1] 00[1] 00[1] 00[1] 00[1] 00[1] 00[1] 03[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1]
[1] PMU5: CAA5 [1] ff[1] ff[1] ff[1] fe[1] 00[1] 00[1] 00[1] 00[1] 00[1] 00[1] 00[1] 03[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1] ff[1]

2) Setting the firmware training to include DQ deskew and CA Training leads to a different error message. 

ddrparam set

TrainCtrl0

0x241f

[1] PMU10: **** Start LPDDR4 Training. PMU Firmware Revision 0x1007 ****
[1] PMU10: Setting boot clock divider to 20
[1] PMU10: PHY TOTALS - NUM_DBYTES 4 NUM_NIBBLES 8 NUM_ANIBS 10
[1] PMU10: CSA=0x03, CSB=0x03, TSTAGES=0x241F, HDTOUT=5, MMISC=0 DRAMFreq=2000MT DramType=LPDDR4
[1] PMU10: Pstate0 MRS MR01_A0=0x34 MR02_A0=0x1B MR03_A0=0x31 MR11_A0=0x35
[1] PMU10: Pstate0 MRS MR12_A0=0x4B MR13_A0=0x00 MR14_A0=0x4B MR22_A0=0x06
[1] PMU10: Pstate0 MRS MR01_A1=0x34 MR02_A1=0x1B MR03_A1=0x31 MR11_A1=0x35
[1] PMU10: Pstate0 MRS MR12_A1=0x4B MR13_A1=0x00 MR14_A1=0x4B MR22_A1=0x06
[1] PMU10: Pstate0 MRS MR01_B0=0x34 MR02_B0=0x1B MR03_B0=0x31 MR11_B0=0x35
[1] PMU10: Pstate0 MRS MR12_B0=0x4B MR13_B0=0x00 MR14_B0=0x4B MR22_B0=0x06
[1] PMU10: Pstate0 MRS MR01_B1=0x34 MR02_B1=0x1B MR03_B1=0x31 MR11_B1=0x35
[1] PMU10: Pstate0 MRS MR12_B1=0x4B MR13_B1=0x00 MR14_B1=0x4B MR22_B1=0x06
[1] End of initialization
[1] End of read enable training
[1] End of fine write leveling
[1] PMU: Error: Dbyte 0 nibble 0 rxClkDly passing region is too small (width = 0)
[1] PMU: ***** Assertion Error - terminating *****
[1] Firmware has failed (firmware completed)

Was the CA Training succesfull now and the bottleneck are the DQ Lanes, here byte 0? Whats nibble 0? 

Schematic and Layout are exact copies of a verified predecessor design. Layerstack differs slightly. Since i reduced the working frequency to 400 MHz and 1000 MHz  i´d rule out a hardware fault. Do you agree ? Attached is the used RPA. 

Best regards

Niko