[LGE-CTO] booting failure with 4G DRAM with OPTE

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[LGE-CTO] booting failure with 4G DRAM with OPTE

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Jessie_Lee
NXP Employee
NXP Employee

Hi @haidong_zheng 

customer is LGE-CTO

project is IFE (In Flight Entertainment)

silicon : i.MX8MQ

BSP : L5.4.70.

issue : customer met booting failure with suck at "starting kernel ...." log.

customer applied below patch and with ddr_timing.c from ddr stress tool.

with below patch + removed OPTEE ==> 4G booting is okay and also 4G memory seems to be okay on target board.

But, below patch + OPTEE , customer met booting failure  with stuck at "starting kernel.." 

diff -urN a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
--- a/arch/arm/dts/imx8mq-evk.dts   2021-01-26 08:40:48.957563246 +0900
+++ b/arch/arm/dts/imx8mq-evk.dts   2021-01-26 08:45:05.274299618 +0900
@@ -29,7 +29,8 @@

    memory@40000000 {
        device_type = "memory";
-       reg = <0x00000000 0x40000000 0 0xc0000000>;
+       reg = <0x0 0x40000000 0 0xc0000000>,
+              <0x1 0x00000000 0 0x40000000>;
    };

    pcie0_refclk: pcie0-refclk {

 

  1. config.h ‘s 4G

diff -urN a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
--- a/configs/imx8mq_evk_defconfig  2021-01-25 10:51:45.397639290 +0900
+++ b/configs/imx8mq_evk_defconfig  2021-01-25 11:31:02.699624338 +0900
@@ -17,6 +17,7 @@
 CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_CSF_SIZE=0x2000
diff -urN a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
--- a/include/configs/imx8mq_evk.h  2021-01-25 10:51:45.489638119 +0900
+++ b/include/configs/imx8mq_evk.h  2021-01-25 11:31:02.783623269 +0900
@@ -171,7 +171,10 @@

 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
-#define PHYS_SDRAM_SIZE            0xC0000000 /* 3GB DDR */
+#define PHYS_SDRAM_SIZE             0xc0000000 /* 3GB */
+#define PHYS_SDRAM_2                0x100000000
+#define PHYS_SDRAM_2_SIZE              0x40000000 /*     */
+

 

below is bdinfo with  booting failure. i am not sure but does below glue text address is as below. it is for your reference. 

u-boot=> bdinfo
arch_number = 0x0000000000000000
boot_params = 0x0000000000000000
DRAM bank = 0x0000000000000000
-> start = 0x0000000040000000
-> size = 0x00000000be000000
DRAM bank = 0x0000000000000001
-> start = 0x0000000100000000
-> size = 0x0000000040000000
baudrate = 115200 bps
TLB addr = 0x00000000fdff0000
relocaddr = 0x00000000fd725000
reloc off = 0x00000000bd525000
irq_sp = 0x00000000fd11c490
sp start = 0x00000000fd11c490
FB base = 0x0000000000000000
Early malloc usage: ae8 / 2000
fdt_blob = 0x00000000fd11c4a8
u-boot=>

 

Could you please check this issue and help me to find any clue?

Thank you

BRs

jessie

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haidong_zheng
NXP Employee
NXP Employee

@Jessie_Lee :

We had a way to support 8MQ 4GB memory without changing OPTEE load address.

Please refer to: https://community.nxp.com/t5/iMX-and-Vybrid-Support/8M-Scale-845-850-board-4GB-memory-support-summar...

 

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203 Views
haidong_zheng
NXP Employee
NXP Employee

@Jessie_Lee :

We had a way to support 8MQ 4GB memory without changing OPTEE load address.

Please refer to: https://community.nxp.com/t5/iMX-and-Vybrid-Support/8M-Scale-845-850-board-4GB-memory-support-summar...

 

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aber
Contributor II

Jessie_Lee :

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Jessie_Lee
NXP Employee
NXP Employee

Hi @haidong_zheng 

Thank you for your help

BRs

jessie

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