LAN9220 with EIM not work properly in i.MX6dq

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LAN9220 with EIM not work properly in i.MX6dq

1,194 Views
rickchu
Contributor IV

Hi,

 

We have SMSC LAN9220 10/100 ethernet controller connected with i.MX6DQ EIM interface; and our design were referenced with "iMax6_EVB sch_SCH-27392.pdf" basically.

But have problem to read/write LAN9220 via EIM interface now. Belows are our configuration in EIM, any suggestions are appreciated.

 

Hardware design:

Reference with pin_connector.jpg. The address has shift 1-bit in lan driver already.

 

EIM configuration:
Reference with EIM_configuration.c

 

Rick

Original Attachment has been moved to: EIM_configuration.c.txt.zip

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10 Replies

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kartjon
Contributor I

can you help me? I do not know why the EIM do not wor on my board.Pin by the oscilloscope, no change. I config and write EIM like the following:

1.config MUX and PAD

static iomux_v3_cfg_t mx6q_sabresd_pads[] = {

                    .

                    .

                    .

/* eim */

        MX6Q_PAD_EIM_OE__WEIM_WEIM_OE,

        MX6Q_PAD_EIM_RW__WEIM_WEIM_RW,

        MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT,

        MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA,

        MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK,

        MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0,

        /* Data Bus */

        MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16,

        MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17,

        MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18,

        MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19,

        MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20,

        MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21,

        MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22,

        MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23,

        MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24,

        MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25,

        MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26,

        MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27,

        MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28,

        MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29,

        MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30,

        MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31,

        /* Address Bus */

        MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15,

        MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14,

        MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13,

        MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12,

        MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11,

        MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10,

        MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9,

        MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8,

        MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7,

        MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6,

        MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5,

        MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4,

        MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3,

        MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2,

        MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1,

        MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0,

};

2.set EIM register

static void mx6q_setup_eim_cs(void)

{

    void __iomem *ram_reg = MX6_IO_ADDRESS(WEIM_BASE_ADDR);

    void __iomem *ccm_reg = MX6_IO_ADDRESS(CCM_BASE_ADDR);

    unsigned int reg;

    struct clk *clk;

    u32 rate;   

    /* CLKCTL_CCGR6: Set emi_slow_clock to be on in all modes */

    reg = readl(ccm_reg + 0x80);

    reg |= 0x00000C00;

    writel(reg, ccm_reg + 0x80);

    clk = clk_get(NULL, "emi_slow_clk");

    if (IS_ERR(clk))

        printk(KERN_ERR "emi_slow_clk not found\n");

    rate = clk_get_rate(clk);

    if (rate != 132000000)

        printk(KERN_ERR "Warning: emi_slow_clk not set to 132 MHz!"

               " WEIM NOR timing may be incorrect!\n");

    writel(0x403304b1, ram_reg);

    writel(0x0, ram_reg + 0x4);

    writel(0x0f010000, ram_reg + 0x8);

    writel(0x00000008, ram_reg + 0xc);

    writel(0x0f040040, ram_reg + 0x10);

    writel(0x00000000, ram_reg + 0x14);

    writel(0x00000000, ram_reg + 0x90);

}

3.iomap(addr:0x08000000, size:0x02000000)

weim->base = devm_ioremap(&pdev->dev, res->start ,len);

            if (weim->base == NULL) {

                    dev_err(&pdev->dev, "Failed to ioremap flash region\n");

                    ret = -EIO;

                    goto weim_err;

            }

4.read and write EIM

long EIM_ioctl(struct file* pFile, unsigned int cmd, unsigned long data)

{

    int val = 0;

    struct eimNode* node = (struct eimNode*)data;

    int *addr = 0;  

    if(weim == 0)

        return FAIL;

    switch(cmd)

    {

    case EIM_READ:

        val = __raw_readl(weim->base + node->offset);

        node->data = val;

        break;

    case EIM_WIRTE:

        __raw_writel(node->data, weim->base + node->offset);

        break;

    default:

        break;

    }

    return SUCCESS;

}

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90 Views
rickchu
Contributor IV

Hi Kart,

Please reference below steps to check with yours.

1. configuration correct IOMUX in hardware platform

2. make sure EMI_SLOW clock has enable for EIM. reference with "18.3.32 CCM Clock Gating Register 6 (CCM_CCGR6) [11:10]"

3. assign address space. reference with "38.3.2 GPR (IOMUXC_IOMUXC_GPR1) [11:10]"

4. adjust timing (depends on your peripheral spec). can reference with 24.9.x

   a. EIM_CSGCR1 and EIM_CSGCR2 for general settings

   b. EIM_CSRCR1 and EIM_CSRCR2 for read timing configuration

   c. EIM_CSWCR1 and EIM_CSWCR2 for write timing configuration

As your hardware using D16~ D31, but I notice that your settings in EIM_CSGCR1[18:16] is 0x3 (32 bit port resides on DATA[31:0]).

Is it typo?

Hope above information will help you figure out the problem.

Rick

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90 Views
kartjon
Contributor I

Thank you Rich!

     The IOMUX and register configuration  as you say. EIM not connected devices,now. I've tried EIM_CSGCR1[18:16] is 0x01、0x02、0x03. Pin by the oscilloscope, no change.

static iomux_v3_cfg_t mx6q_sabresd_pads[] = {

  /* AUDMUX */

  MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC,

  MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD,

  MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS,

  MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD,

  /* CAN1  */

  MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE,

  /* MX6Q_PAD_KEY_COL2__CAN1_TXCAN, */

  MX6Q_PAD_GPIO_1__WDOG2_WDOG_B, /*WDOG_B to reset pmic*/

  MX6Q_PAD_GPIO_2__GPIO_1_2, /* user defined red led */

  MX6Q_PAD_GPIO_7__GPIO_1_7, /* NERR */

  /* CCM  */

  MX6Q_PAD_GPIO_0__CCM_CLKO, /* SGTL500 sys_mclk */

  MX6Q_PAD_GPIO_3__CCM_CLKO2, /* J5 - Camera MCLK */

  /* ECSPI1 */

  MX6Q_PAD_KEY_COL0__ECSPI1_SCLK,

  MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI,

  MX6Q_PAD_KEY_COL1__ECSPI1_MISO,

  MX6Q_PAD_KEY_ROW1__GPIO_4_9,

  /* ENET */

  MX6Q_PAD_ENET_MDIO__ENET_MDIO,

  MX6Q_PAD_ENET_MDC__ENET_MDC,

  MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,

  MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,

  MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,

  MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,

  MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,

  MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,

  MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,

  MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,

  MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,

  MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,

  MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,

  MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,

  MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,

  MX6Q_PAD_ENET_TX_EN__GPIO_1_28, /* Micrel RGMII Phy Interrupt */

  MX6Q_PAD_EIM_D23__GPIO_3_23, /* RGMII reset */

  MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT, /* Internal connect for 1588 TS Clock */

  /* GPIO1 */

  MX6Q_PAD_ENET_RX_ER__GPIO_1_24, /* J9 - Microphone Detect */

  /* GPIO2 */

  /* MX6Q_PAD_NANDF_D1__GPIO_2_1,*/ /* J14 - Menu Button */

  /* MX6Q_PAD_NANDF_D2__GPIO_2_2,*/ /* J14 - Back Button */

  /* MX6Q_PAD_NANDF_D3__GPIO_2_3,*/ /* J14 - Search Button */

  /* MX6Q_PAD_NANDF_D4__GPIO_2_4,*/ /* J14 - Home Button */

  MX6Q_PAD_EIM_A22__GPIO_2_16, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_A21__GPIO_2_17, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_A20__GPIO_2_18, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_A19__GPIO_2_19, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_A18__GPIO_2_20, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_A17__GPIO_2_21, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_A16__GPIO_2_22, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_RW__GPIO_2_26, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_LBA__GPIO_2_27, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_EB0__GPIO_2_28, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_EB1__GPIO_2_29, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_EB3__GPIO_2_31, /* J12 - Boot Mode Select */

  /* GPIO3 */

  MX6Q_PAD_EIM_DA0__GPIO_3_0, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_DA1__GPIO_3_1, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_DA2__GPIO_3_2, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_DA3__GPIO_3_3, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_DA4__GPIO_3_4, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_DA5__GPIO_3_5, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_DA6__GPIO_3_6, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_DA7__GPIO_3_7, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_DA8__GPIO_3_8, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_DA9__GPIO_3_9, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_DA10__GPIO_3_10, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_DA11__GPIO_3_11, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_DA12__GPIO_3_12, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_DA13__GPIO_3_13, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_DA14__GPIO_3_14, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_DA15__GPIO_3_15, /* J12 - Boot Mode Select */

  /* SW4 , SW5 & SW1 */

  MX6Q_PAD_GPIO_4__GPIO_1_4, /* Volume Up */

  MX6Q_PAD_GPIO_5__GPIO_1_5, /* Volume Down */

  MX6Q_PAD_EIM_D29__GPIO_3_29, /* power off */

  /* CAP_TCH_INT1 */

  MX6Q_PAD_NANDF_CLE__GPIO_6_7,

  /* CAP_TCH_INT0 */

  MX6Q_PAD_NANDF_ALE__GPIO_6_8,

  /* eCompass int */

  MX6Q_PAD_EIM_D16__GPIO_3_16,

  /* GPIO5 */

  MX6Q_PAD_EIM_WAIT__GPIO_5_0, /* J12 - Boot Mode Select */

  MX6Q_PAD_EIM_A24__GPIO_5_4, /* J12 - Boot Mode Select */

  /* GPIO6 */

  MX6Q_PAD_EIM_A23__GPIO_6_6, /* J12 - Boot Mode Select */

  MX6Q_PAD_NANDF_RB0__GPIO_6_10, /* AUX_5V Enable */

  /* I2C1, WM8958 */

  MX6Q_PAD_CSI0_DAT8__I2C1_SDA,

  MX6Q_PAD_CSI0_DAT9__I2C1_SCL,

  /* I2C2, Camera, MIPI */

  MX6Q_PAD_KEY_COL3__I2C2_SCL,

  MX6Q_PAD_KEY_ROW3__I2C2_SDA,

#ifdef CONFIG_MX6_ENET_IRQ_TO_GPIO

  MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1,

#else

  /* I2C3 */

  MX6Q_PAD_GPIO_3__I2C3_SCL, /* GPIO1[3] */

  MX6Q_PAD_GPIO_6__I2C3_SDA,

#endif

  /* DISPLAY */

  MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,

  MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DE */

  MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSync */

  MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSync */

  MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4, /* Contrast */

  MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,

  MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,

  MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,

  MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,

  MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,

  MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,

  MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,

  MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,

  MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,

  MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,

  MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,

  MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,

  MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,

  MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,

  MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,

  MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,

  MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,

  MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,

  MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,

  MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,

  MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,

  MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,

  MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,

  MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,

  MX6Q_PAD_GPIO_7__GPIO_1_7, /* J7 - Display Connector GP */

  MX6Q_PAD_GPIO_9__GPIO_1_9, /* J7 - Display Connector GP */

  /* MX6Q_PAD_NANDF_D0__GPIO_2_0,*/ /* J6 - LVDS Display contrast */

  /* DISP_PWM */

  MX6Q_PAD_SD1_DAT3__PWM1_PWMO, /* GPIO1[21] */

  /* UART1 for debug */

  MX6Q_PAD_CSI0_DAT10__UART1_TXD,

  MX6Q_PAD_CSI0_DAT11__UART1_RXD,

  /* UART3 for gps */

  MX6Q_PAD_EIM_D24__UART3_TXD,

  MX6Q_PAD_EIM_D25__UART3_RXD,

  /* USBOTG ID pin */

  MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID,

  /* USB power pin */

  MX6Q_PAD_EIM_D22__GPIO_3_22,

  MX6Q_PAD_ENET_TXD1__GPIO_1_29,

  /* USB OC pin */

  MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC,

  MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC,

  /* USDHC2 */

  MX6Q_PAD_SD2_CLK__USDHC2_CLK,

  MX6Q_PAD_SD2_CMD__USDHC2_CMD,

  MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,

  MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,

  MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,

  MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,

  MX6Q_PAD_NANDF_D4__USDHC2_DAT4,

  MX6Q_PAD_NANDF_D5__USDHC2_DAT5,

  MX6Q_PAD_NANDF_D6__USDHC2_DAT6,

  MX6Q_PAD_NANDF_D7__USDHC2_DAT7,

  MX6Q_PAD_NANDF_D2__GPIO_2_2, /* SD2_CD */

  MX6Q_PAD_NANDF_D3__GPIO_2_3, /* SD2_WP */

  /* USDHC3 */

  MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ,

  MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ,

  MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ,

  MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ,

  MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ,

  MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ,

  MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ,

  MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ,

  MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ,

  MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ,

  MX6Q_PAD_NANDF_D0__GPIO_2_0, /* SD3_CD */

  MX6Q_PAD_NANDF_D1__GPIO_2_1, /* SD3_WP */

  /* USDHC4 */

  MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ,

  MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ,

  MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ,

  MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ,

  MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ,

  MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ,

  MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ,

  MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ,

  MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ,

  MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ,

  /* Charge */

  MX6Q_PAD_EIM_A25__GPIO_5_2,  /* FLT_1_B */

  MX6Q_PAD_EIM_D23__GPIO_3_23, /* CHG_1_B */

  MX6Q_PAD_EIM_DA13__GPIO_3_13, /* CHG_2_B  */

  MX6Q_PAD_EIM_DA14__GPIO_3_14, /* FLT_2_B */

  MX6Q_PAD_ENET_RXD0__GPIO_1_27, /* UOK_B */

  MX6Q_PAD_EIM_CS1__GPIO_2_24,   /* DOK_B */

  /* Audio Codec */

  MX6Q_PAD_KEY_COL2__GPIO_4_10, /* CODEC_PWR_EN */

  MX6Q_PAD_SD3_RST__GPIO_7_8, /* HEADPHONE_DET */

  MX6Q_PAD_GPIO_9__GPIO_1_9, /* MICROPHONE_DET */

  /*GPS AUX_3V15_EN*/

  MX6Q_PAD_NANDF_WP_B__GPIO_6_9,

  /* PCIE */

  MX6Q_PAD_EIM_D19__GPIO_3_19, /* PCIE_PWR_EN */

  MX6Q_PAD_GPIO_17__GPIO_7_12, /* PCIE_RST */

  MX6Q_PAD_KEY_COL4__GPIO_4_14, /* PCIE_DIS */

  /* DISP_RST_B */

  MX6Q_PAD_NANDF_CS0__GPIO_6_11,

  /* DISP_PWR_EN */

  MX6Q_PAD_NANDF_CS1__GPIO_6_14,

  /* CABC_EN0 */

  MX6Q_PAD_NANDF_CS2__GPIO_6_15,

  /* CABC_EN1 */

  MX6Q_PAD_NANDF_CS3__GPIO_6_16,

  /* eim */

  MX6Q_PAD_EIM_OE__WEIM_WEIM_OE,

  MX6Q_PAD_EIM_RW__WEIM_WEIM_RW,

  MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT,

  MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA,

  MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK,

  MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0,

        MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16,

        MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17,

        MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18,

        MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19,

        MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20,

        MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21,

        MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22,

        MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23,

        MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24,

        MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25,

        MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26,

        MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27,

        MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28,

        MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29,

        MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30,

        MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31,

        MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23,

        MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22,

        MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21,

        MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20,

        MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19,

        MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18,

        MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17,

        MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16,

        MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15,

        MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14,

        MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13,

        MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12,

        MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11,

        MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10,

        MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9,

        MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8,

        MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7,

        MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6,

        MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5,

        MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4,

        MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3,

        MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2,

        MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1,

        MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0,

};

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kitty
Contributor I

hello Rick,

I have problem to read/write 16C554 via EIM interface now,I have seen your  configuration in EIM.I operate 16c554 using EIM_CS0, you and me have a similar configuration, but now EIM can not be properly read and write operations. Read manuals, did not find the reason. You solved this problem yet? This problem does not know if you have any good ideas, hoping to get your help, thank you!

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rickchu
Contributor IV

Hello Li Ming,

In my suggestion, you can check with below items step by step.

1. Make sure all IOMUX configurations are correct. You can use "IOMux Tool (can download from freescale web site)" to help verify if configuration conflict.

2. Due to some of PINs are used for device boot up detect at the same time, so you have to measure all of address and data pins signal with oscilloscope, and make sure all of they are correct.

3. Adjust EIM configuration to meet 16C554 timing chart.

Good luck.

Rick

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kitty
Contributor I

hello Rick,

Thank you for your help! According to what you said step, I'm trying to do it. My first step is to do like this:

1 .In the "linux/arch/arm/mach-mx6/board-mx6dl_sabresd.h" file added these codes:

static iomux_v3_cfg_t mx6dl_sabresd_eim_pads[] = {

        MX6DL_PAD_EIM_CS0__WEIM_WEIM_CS_0 , //CS0

        MX6DL_PAD_EIM_OE__WEIM_WEIM_OE,     //OE

        MX6DL_PAD_EIM_RW__WEIM_WEIM_RW,     //RW

        MX6DL_PAD_CSI0_DAT12__WEIM_WEIM_D_8,//D8

        MX6DL_PAD_CSI0_DAT13__WEIM_WEIM_D_9,//D9

        MX6DL_PAD_CSI0_DAT14__WEIM_WEIM_D_10,//D10

        MX6DL_PAD_CSI0_DAT15__WEIM_WEIM_D_11,//D11

        MX6DL_PAD_CSI0_DAT16__WEIM_WEIM_D_12,//D12

        MX6DL_PAD_CSI0_DAT17__WEIM_WEIM_D_13,//D13

        MX6DL_PAD_CSI0_DAT18__WEIM_WEIM_D_14,//D14

        MX6DL_PAD_CSI0_DAT19__WEIM_WEIM_D_15,//D15

        MX6DL_PAD_EIM_DA0__WEIM_WEIM_DA_A_0, //DA0

        MX6DL_PAD_EIM_DA1__WEIM_WEIM_DA_A_1, //DA1

        MX6DL_PAD_EIM_DA2__WEIM_WEIM_DA_A_2, //DA2

        MX6DL_PAD_EIM_DA3__WEIM_WEIM_DA_A_3, //DA3

        MX6DL_PAD_EIM_DA4__WEIM_WEIM_DA_A_4, //DA4

        MX6DL_PAD_EIM_A23__WEIM_WEIM_A_23,   //A23

        MX6DL_PAD_EIM_A22__WEIM_WEIM_A_22,   //A22

        MX6DL_PAD_EIM_DA9__GPIO_3_9,         //GPIO3[9]   gpio-interrupt

        MX6DL_PAD_EIM_CS1__GPIO_2_24,        //GPIO2[24]   gpio-interrupt

        MX6DL_PAD_EIM_DA15__GPIO_3_15,       //GPIO3[15]   gpio-interrupt

        MX6DL_PAD_EIM_D16__GPIO_3_16,       //GPIO3[16]       gpio-interrupt

        MX6DL_PAD_EIM_D23__GPIO_3_23,      //GPIO3[23]        gpio-interrupt

        MX6DL_PAD_EIM_D19__GPIO_3_19,     //GPIO3[19]          gpio-interrupt

        MX6DL_PAD_EIM_DA13__GPIO_3_13,   //GPIO3[13]          gpio-interrupt

        @MX6DL_PAD_EIM_DA14__GPIO_3_14,  //GPIO3[14]         gpio-interrupt

};

2. In "Linux/arch/arm/mach-mx6/board-mx6q_sabresd.c" file to initialize:

mxc_iomux_v3_setup_multiple_pads(mx6dl_sabresd_eim_pads,

            ARRAY_SIZE(mx6dl_sabresd_eim_pads));

     I do not know whether this approach is feasible, the idea is correct?You said IOMUX TOOL, I was studying with  it and hope to find something valuable. The first use of Freescale products have a lot of places are not too clear, I hope we jointly explore and improve together, and look forward to your reply, in thanks for your help!

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rickchu
Contributor IV

Hi Li Ming,

I just start porting i.MX6DQ platform on June, as not much experience just like you. Hope below information helpful to you.

----

Your IOMUX configurations are correct, and you may need to check EIM_CS0GCR1 (application processors reference manual page CH 24.101.1).

In your hardware design, the address and data are independent, so you don't need enable MUM[3] (mulitplexed mode) as mime.

For quickly debug, you can do while-loop (A[2:0]=0x7, D[7:0]=0x3F) in your driver, and to monitor all signals (address and data pins) correct or not.

Good luck,

Rick

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kitty
Contributor I

hello Rick,

Thank you for your help!Under your guidance,now I can test to CS0 signal, thank your very much! But I have two questions still need to ask you:

1.registers  EIM_CSnRCR1 and EIM_CSnWCR1  of the "ADV signal (RADVA / RADVN) "refers to what, I don't understand;

2.When I put the pin is set to EIM mode, if I want to do an assignment for a pin, that how to do? Do you need to turn it into GPIO mode, for example, I want to D [7 ... 0] assignment, then how to do?

Looking forward to your reply!

Li

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rickchu
Contributor IV

Hi Li,

1) Depends on what operating modes that you usage (reference Table 24-6), and then reference with Figure 24-4.

    EIM_CSnRCR1 and EIM_CSRCR2 are relatives with read timing; EIM_CSnWCR1 and EIM_CSnWCR2 are relatives with write timing.

    You have to understand what r/w timing requirement in ST16554, and then adjust EIM parameters to communication with it.

2) Can not understand your question.

Rick

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rickchu
Contributor IV

The issue has been fixed. To fixed it by modify hardware resistor between EIM_DAx and BOOT_CFGx.