KSZ9131RNX Porting to i.MX8

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KSZ9131RNX Porting to i.MX8

5,598 Views
neil_chang
Contributor I

Hi

we are using microchip KSZ9131RNX as our ethernet phy,according to i.MX reference user manual

the fec driver will auto-probes the external adaptor (PHY device).but we can not probe KSZ9131

Is there any config or driver we need to porting to i.MX8mq platform?

Thanks

Neil

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20 Replies

1,933 Views
mdonahoe
Contributor III

What is .config_aneg  getting set to for ksz9131 in the ksphy_driver array?  Should be able to use KSZ9031 as a reference.



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4,451 Views
khang_letruong
Senior Contributor III

@Hi @neil_chang ,

I'm not sure if the issue has already been solved but Toradex does use KSZ9131 in their boards : http://git.toradex.com/cgit/linux-toradex.git/log/?h=toradex_4.14-2.0.x-imx-next

We use this driver for our customized iMX8 M Plus (rev A0) board and it works. 

Regards,
Khang

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5,088 Views
neil_chang
Contributor I

Hi igor

currently our KSZ9131 driver will try to init

but cause kernel panic

[ 13.787983] Microchip KSZ9131 Gigabit PHY 30be0000.ethernet-1:00: attached PHY driver [Microchip KSZ9131 Gigabit PHY] (mii_bus:phy_addr=30be0000.ethernet-1:00, irq=POLL)
[ 13.803199] Unable to handle kernel NULL pointer dereference at virtual address 00000000

Do you know what happen?

Thanks

Neil

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5,087 Views
igorpadykov
NXP Employee
NXP Employee

Hi Neil

error "Unable to handle kernel NULL pointer dereference at virtual address 00000000"

usually points to ddr errors. Suggest to run ddr test and update image with new ddr

calibration coefficients.

Best regards
igor

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5,087 Views
neil_chang
Contributor I

Hi igor

we have done the DDR test, there is nothing fail

Downloading file 'bin\lpddr4_train1d_string.bin' ..Done

Downloading file 'bin\lpddr4_train2d_string.bin' ..Done

Downloading file 'bin\lpddr4_pmu_train_1d_imem.bin' ..Done

Downloading file 'bin\lpddr4_pmu_train_1d_dmem.bin' ..Done

Downloading file 'bin\lpddr4_pmu_train_2d_imem.bin' ..Done

Downloading file 'bin\lpddr4_pmu_train_2d_dmem.bin' ..Done

Downloading IVT header...Done
Downloading file 'bin\m850_ddr_stress_test.bin' ...Done

Download is complete
Waiting for the target board boot...

********Found PMIC PF0100**********

*************************************************************************

*************************************************************************

*************************************************************************
MX8 DDR Stress Test V3.00
Built on Dec 9 2019 13:45:27
*************************************************************************

--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x91d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122

- MMU and cache setup complete

*************************************************************************
ARM clock(CA53) rate: 800MHz
DDR Clock: 1600MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 16, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 2048MB
Density per controller is: 2048MB
Total density detected on the board is: 2048MB
============================================

MX8M: Cortex-A53 is found

*************************************************************************

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @1600Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @200Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @50Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @1600Mhz...
[Process] End of initialization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Result] PASS

============ Step 2: DDR memory accessing... ============
Verifying DDR frequency point0@1600MHz.......Pass
Verifying DDR frequency point1@200MHz.......Pass
Verifying DDR frequency point2@50MHz.......Pass
[Result] OK

============ Step 3: DDR parameters processing... ============
[Result] Done

Success: DDR Calibration completed!!!
DDR Stress Test Iteration 1
--------------------------------
--Running DDR test on region 1--
--------------------------------

t0.1: data is addr test
....
t0.2: row hop read test
...

t1: memcpy SSN armv8_x32 test
....
t2: byte-wise SSN armv8_x32 test
..
t3: memcpy pseudo random pattern test
....................................................................
t4: IRAM_to_DDRv1 test
...

t5: IRAM_to_DDRv2 test
--------------------------------
--Running DDR test on frequency point1@200MHz--
--------------------------------

t0.1: data is addr test
....
t0.2: row hop read test
...

t1: memcpy SSN armv8_x32 test
....
t2: byte-wise SSN armv8_x32 test
..
t3: memcpy pseudo random pattern test
....................................................................
t4: IRAM_to_DDRv1 test
...

t5: IRAM_to_DDRv2 test
--------------------------------
--Running DDR test on frequency point2@50MHz--
--------------------------------

t0.1: data is addr test
....
t0.2: row hop read test
...

t1: memcpy SSN armv8_x32 test
....
t2: byte-wise SSN armv8_x32 test
..
t3: memcpy pseudo random pattern test
....................................................................
t4: IRAM_to_DDRv1 test
...

t5: IRAM_to_DDRv2 test

Success: DDR Stress test completed!!!

Thanks

Neil

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5,089 Views
igorpadykov
NXP Employee
NXP Employee

one can try to find place where panic occurs using

AN4553 Using Open Source Debugging Tools for Linux on i.MX Processors
https://www.nxp.com/docs/en/application-note/AN4553.pdf

Best regards
igor

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5,088 Views
neil_chang
Contributor I

Hi igor

we use nxp_imx-p9.0.0_2.3.0

Thanks

Neil

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igorpadykov
NXP Employee
NXP Employee

as this android release is based on L4.14.98-2.1.0 suggest first

to test in uboot

imx8mq_evk.c\imx8mq_evk\freescale\board - uboot-imx - i.MX U-Boot 

check enet clock with oscilloscope in function  setup_fec( )

Best regards
igor

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5,088 Views
neil_chang
Contributor I

hi igor

we can not measure the enet clock with oscilloscope

Do we need check others?

Thanks

Neil

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igorpadykov
NXP Employee
NXP Employee

is board able to boot? If yes could you provde full log.

Best regards
igor

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5,089 Views
neil_chang
Contributor I

Hi igor

it can boot,please help us to check log

Thanks

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5,089 Views
neil_chang
Contributor I

Hi igor

This is our phy setting in device tree

&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_reset>;
assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
<&clk IMX8MQ_CLK_ENET_TIMER>,
<&clk IMX8MQ_CLK_ENET_REF>,
<&clk IMX8MQ_CLK_ENET_TIMER>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_SYS2_PLL_100M>,
<&clk IMX8MQ_SYS2_PLL_125M>;
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
phy-reset-gpios = <&gpio1 9 0>;
fsl,magic-packet;
status = "okay";

mdio {
#address-cells = <1>;
#size-cells = <0>;

ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};

Is there any config missing?

Thanks

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igorpadykov
NXP Employee
NXP Employee

one can try to check i.MX8MQ ENET clocks running in parallel

non working board and i.MX8MQ EVK and check ENET registers in

uboot setup_fec():

in particular IOMUXC_GPR_GPR1 described in sect.8.2.4.2 GPR1

General Purpose Register (IOMUXC_GPR_GPR1) i.MX8MQ Reference Manual

check ENET clock with oscilloscope in both cases.


Best regards
igor

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5,089 Views
neil_chang
Contributor I

according to this thread Porting KSZ9031 to i.MX BSP 

Do we need to change clocks as below?

assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
<&clk IMX8MQ_CLK_ENET_TIMER>,
<&clk IMX8MQ_CLK_ENET_REF>,
<&clk IMX8MQ_CLK_ENET_TIMER>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_SYS2_PLL_100M>,
<&clk IMX8MQ_SYS2_PLL_250M>;

in imx8mq_evk.c

static int setup_fec(void)
{
struct iomuxc_gpr_base_regs *iomuxc_gpr_regs
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;

setup_iomux_fec();

printf("iomux gpr1 is %u \n",iomuxc_gpr_regs->gpr[1]);
/* Use 125M anatop REF_CLK1 for ENET1, not from external */
//clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
//IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], BIT(13) | BIT(17), 0);

printf("after set iomux gpr1 is %u \n",iomuxc_gpr_regs->gpr[1]);
return set_clk_enet(ENET_125MHZ);
}

it can only set clock to 125MHz

can you help us check?

Thanks

Neil

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neil_chang
Contributor I

Hi igor 

we have no test pad on i.MX8 EVK,so we cannot check ENET CLOCK on EVK

Thanks

Neil

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5,089 Views
igorpadykov
NXP Employee
NXP Employee

however you can printf IOMUXC_GPR_GPR1 register in both cases

Best regards
igor

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5,089 Views
neil_chang
Contributor I

Hi igor

I have read the gpr1 reg as below

set_clk_enet(ENET_125MHZ);
printf(" set iomux gpr1 is %u \n",iomuxc_gpr_regs->gpr[1]);

the result is both 0 

can you give us more hint about this reg

Thanks

Neil

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5,088 Views
neil_chang
Contributor I

Hi igor

we use i.MX8MQ and use 1.8V with KSZ9131

I have applied this patch in Kernel not uboot

But still cannot find eth0

Thanks

Neil

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igorpadykov
NXP Employee
NXP Employee

Hi Neil

what software used in the case, please try with nxp from:

source.codeaurora.org/external/imx/linux-imx  repository

uboot-imx - i.MX U-Boot

Best regards
igor

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5,088 Views
igorpadykov
NXP Employee
NXP Employee

Hi Neil

what i.MX8 processor used in the case (there are i.MX8MQ and i.MX8QM references,

they are different processors). One can start with checking hardware:

look at supported enet voltages in i.MX8 datasheets i.MX 8 Series Applications Processors | Arm® Cortex®-A72/A53/A35/M4 cores | NXP 

KSZ9131 supports 3.3V/2.5V/1.8V.

As for software check if patch is applied

[net] net: phy: micrel: add Microchip KSZ9131 inital driver - Patchwork 

May be recommended first to check if it works in uboot:

uboot-imx - i.MX U-Boot 

Best regards
igor
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