KSZ8081 not probing on i.MX8M Mini

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KSZ8081 not probing on i.MX8M Mini

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986 Views
namanthaker
Contributor IV

Hello,

I am trying to integrate KSZ8081 Ethernet PHY on i.MX8M Mini with Yocto L5.4.47-2.2.0.

Below are my DTS settings:

 

&fec1 {                                                           
        pinctrl-names = "default";                                
        pinctrl-0 = <&pinctrl_fec1>;                              
        phy-mode = "rmii";                                        
        phy-handle = <&ethphy0>;                                  
        fsl,magic-packet;                                         
        phy-reset-gpios = <&gpio1 1 0>;                           
        status = "okay";                                          
                                                                  
        mdio {                                                    
                #address-cells = <1>;                             
                #size-cells = <0>;                                
                                                                  
                ethphy0: ethernet-phy@1 {                         
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <1>;   // PHY ADDRESS = 1
                };                                                
        };                                                        
};                                                                

pinctrl_fec1: fec1grp {                                             
        fsl,pins = <                                                
                MX8MM_IOMUXC_ENET_MDC_ENET1_MDC         0x3         
                MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO       0x23        
                MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK      0x4000001f  
                MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x56        
                MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x56        
                MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x56        
                MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x56        
                MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER       0x56        
                MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x56
                MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x56
        >;                                                          
};                                                                  

fec1: ethernet@30be0000 {                                
        compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
        reg = <0x30be0000 0x10000>;                      
        interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,  
                     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,  
                     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;  
        clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,           
                 <&clk IMX8MM_CLK_ENET1_ROOT>,           
                 <&clk IMX8MM_CLK_ENET_TIMER>,           
                 <&clk IMX8MM_CLK_ENET_REF>,             
                 <&clk IMX8MM_CLK_ENET_PHY_REF>;         
        clock-names = "ipg", "ahb", "ptp",               
                      "enet_clk_ref", "enet_out";        
        assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,    
                          <&clk IMX8MM_CLK_ENET_TIMER>,  
                          <&clk IMX8MM_CLK_ENET_REF>,    
                          <&clk IMX8MM_CLK_ENET_TIMER>;  
        assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
                                 <&clk IMX8MM_SYS_PLL2_100M>,
                                 <&clk IMX8MM_SYS_PLL2_50M>;
        assigned-clock-rates = <0>, <0>, <50000000>, <100000000>;
        fsl,num-tx-queues = <3>;                         
        fsl,num-rx-queues = <3>;                         
        nvmem-cells = <&fec_mac_address>;                
        nvmem-cell-names = "mac-address";                
        nvmem_macaddr_swap;                              
        stop-mode = <&gpr 0x10 3>;                       
        fsl,wakeup_irq = <2>;                            
        status = "disabled";                             
};                                                       

 

I made below changes in u-boot to get 50Mhz clock from MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK pin.

diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c
index af15998..a1f3f42 100644                                                    
--- a/board/freescale/imx8mm_evk/imx8mm_evk.c                                    
+++ b/board/freescale/imx8mm_evk/imx8mm_evk.c                                    
@@ -91,9 +91,13 @@ static int setup_fec(void)                                    
                (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;             
                                                                                 
        /* Use 125M anatop REF_CLK1 for ENET1, not from external */              
-       clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);                                
+//     clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);                                
                                                                                 
-       return 0;                                                                
+       setbits_le32(&gpr->gpr[1],                                               
+                       IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);              
+                                                                                
+       return set_clk_enet(ENET_50MHZ);                                         
}

In the kernel logs I get generic PHY as below instead of KSZ8081:
[ 6.073108] Generic PHY 30be0000.ethernet-1:01: attached PHY driver [Generic PHY] (mii_bus:phy_addr=30be0000.ethernet-1:01, irq=POLL)

It seems the host processor is unable to read the KSZ8081 phy id in get_phy_id function in drivers/net/phy/phy_device.c. I put below logs in phy_device.c

diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index c3ebbfe..623e070 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -807,6 +817,7 @@ static int get_phy_id(struct mii_bus *bus, int addr, u32 *phy_id,
 
        *phy_id |= phy_reg;
 
+       printk(KERN_ERR "%s: phy_id=0x%x\n", __func__, *phy_id);
        return 0;
 }

I am getting below logs:

[ 1.305494] get_phy_id: phy_id=0xffffffff
[ 1.312751] get_phy_id: phy_id=0xffffffff
[ 1.319998] get_phy_id: phy_id=0xffffffff
[ 1.327248] get_phy_id: phy_id=0xffffffff
[ 1.334490] get_phy_id: phy_id=0xffffffff
[ 1.341748] get_phy_id: phy_id=0xffffffff
[ 1.348999] get_phy_id: phy_id=0xffffffff
[ 1.356244] get_phy_id: phy_id=0xffffffff
[ 1.363523] get_phy_id: phy_id=0xffffffff
[ 1.370766] get_phy_id: phy_id=0xffffffff
[ 1.378014] get_phy_id: phy_id=0xffffffff
[ 1.385265] get_phy_id: phy_id=0xffffffff
[ 1.392513] get_phy_id: phy_id=0xffffffff
[ 1.399761] get_phy_id: phy_id=0xffffffff
[ 1.407007] get_phy_id: phy_id=0xffffffff
[ 1.414250] get_phy_id: phy_id=0xffffffff
[ 1.421497] get_phy_id: phy_id=0xffffffff
[ 1.428744] get_phy_id: phy_id=0xffffffff
[ 1.435993] get_phy_id: phy_id=0xffffffff
[ 1.443244] get_phy_id: phy_id=0xffffffff
[ 1.450485] get_phy_id: phy_id=0xffffffff
[ 1.457735] get_phy_id: phy_id=0xffffffff
[ 1.464982] get_phy_id: phy_id=0xffffffff
[ 1.472229] get_phy_id: phy_id=0xffffffff
[ 1.479478] get_phy_id: phy_id=0xffffffff
[ 1.486721] get_phy_id: phy_id=0xffffffff
[ 1.493969] get_phy_id: phy_id=0xffffffff
[ 1.501217] get_phy_id: phy_id=0xffffffff
[ 1.508464] get_phy_id: phy_id=0xffffffff
[ 1.515711] get_phy_id: phy_id=0xffffffff
[ 1.522958] get_phy_id: phy_id=0xffffffff
[ 1.530201] get_phy_id: phy_id=0xffffffff
[ 2.807197] get_phy_id: phy_id=0x0

I have checked that all the power signals to KSZ8081 PHY are correct and the reset line is high (the power sequence is correct). The 50Mhz clock is also recevied properly from ENET_TD2 pin.
Just to make sure, I also connected a external oscillator to KSZ8081 instead of ENET_TD2, but the PHY ID is not read successfully.

Please help me to get KSZ8081 probed on i.MX8MM.

Thanks in advance.

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1 Solution
869 Views
namanthaker
Contributor IV

After a lot of debugging, I got the KSZ8081 detected and working by using below pinctrls configurations:

pinctrl_fec1: fec1grp {
	fsl,pins = <
		MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
		MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
		MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK		0x4000001f
		MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
		MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
		MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
		MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
		MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER		0x1f
		MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER		0x91
		MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x1f
		MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x91
	>;
};

 

Regards,
Naman

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3 Replies
870 Views
namanthaker
Contributor IV

After a lot of debugging, I got the KSZ8081 detected and working by using below pinctrls configurations:

pinctrl_fec1: fec1grp {
	fsl,pins = <
		MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
		MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
		MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK		0x4000001f
		MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
		MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
		MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
		MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
		MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER		0x1f
		MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER		0x91
		MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x1f
		MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x91
	>;
};

 

Regards,
Naman

963 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi Naman

 

one can check phy initialization as in example below, function board_eth_init() and phy PHYAD[2:0] address defined by strap-in pins
https://source.codeaurora.org/external/imx/uboot-imx/tree/board/technexion/pico-imx6ul/pico-imx6ul.c...

 

Best regards
igor

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939 Views
namanthaker
Contributor IV

Hi Igor,

Thank you for looking into this.

I have checked the PHY initialization timing of reset and it is same as mentioned in the suggested link. The reset timing and PHYAD are correct for KSZ8081.

To debug this issue, I have verified below points:
1) All power supplies are measured and found okay.
- VDDA_3V3 = 3.3V
- VDDIO = 1.8V
2) I have given 50MHz clock on pin 9(XI) through crystal oscillator and it is coming okay.
3) Reset signal is coming okay (It is initial low and then going high after all power supplies are stable). The timing of reset is same as used in the above link.
4) I have measured frequency on MDC line which is 2.5MHz. Also, on MDIO line, data is observed using oscilloscope.

All these measurements are found to be okay but still I are not able to read PHY ID on MDIO lines.

I have attached KSZ8081 schematic for reference.

Regards,
Naman

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